How to print enumerated signal to file in VHDL testbench?

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design_engineer

Joined: 23 Oct 2006
Posts: 11

07 Mar 2008 21:17 How to print enumerated signal to file in VHDL testbench?

Hello,

I have a signal defined as an enumerated type in my design.

type state is (idle, start, run, end);
signal t_state is array (3 downto 0) of state;

How do I print the value of this signal to a file during my simulation?

When I do

write(line_out, t_state) or write(line_out, t_state(0))

I get argument type mismatch error during compilation.

Please help.

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shawndaking

Joined: 20 Jun 2001
Posts: 235
Helped: 6

09 Mar 2008 13:06 Re: How to print enumerated signal to file in VHDL testbench

you can assign values to everything :

for example :

dbg_p : process (clk)
begin
if rising_edge(clk) then
new_arb_sm_dff <= new_arb_sm;
case new_arb_sm_dff is
when IDLE => pkt_arb_state_dbg <= "000";
when NPI_REQ => pkt_arb_state_dbg <= "001";
when GNT_ASI_0 => pkt_arb_state_dbg <= "010";
when GNT_ASI_1 => pkt_arb_state_dbg <= "011";
when GNT_IP => pkt_arb_state_dbg <= "100";
end case;
end if;
end process dbg_p;