guard rings documentation

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alecsander

Joined: 07 Jun 2007
Posts: 28

28 Feb 2008 15:52 guard ring for silicon die

Hi!

I have a question about layouting the guard rings in CMOS technology. n+ or p+ guard rings are connected to power or ground.
Hastings of other books speaks only in general about these rings. But i have some small issues that i cannot find in books:
- how can i dimension the guard ring, not to be too thin, but also not to big?
- the metal of the guard ring must be cut? Some currents appear, and a current loop may form.
In general , can somebody help me with some advanced documentation on guard rings?

Thx,Alex.

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varma_cs012

Joined: 22 Jan 2008
Posts: 87
Helped: 7
Location: Hyderabad

29 Feb 2008 5:01 single versus double guard ring layout

Alex,

May I know you are asking about Tap or Guardring ?
Then we can discuss about this in detail.

alecsander

Joined: 07 Jun 2007
Posts: 28

29 Feb 2008 13:28 triple guard ring layout

Hi!

No, i'm not asking about tap guard rings. I'm asking about a guard ring surrounding a digital cell that is really noisy and must be isolated. I read that the disturber must be surrounded by n+ guard ring connected to it's own supply, and that the disturbed cell mult be surrounded by p+ guard ring connected to GND. But i cannot find anywhere some details about constructing guard rings, i mean how wide, how many rows of contacts, why and where should the metal be cut ... and maybe more. The simple : make 3 rows of contacts, place 'em in a Nwell and cut them at the oposite corner from the supply doesn't satisfy me. It may be true ... but why? Very Happy

fixrouter4400

Joined: 06 Feb 2007
Posts: 199
Helped: 23

29 Feb 2008 14:35 guard ring

Hi alecsander,

In constructing a P+ guardring these are the layers you will need PP/OD/M1/CO same is true in making an N+ guardring NP/OD/M1/CO.

The easiest way to make your guardring e.g. P+ build a single p+ contact following your design rule then you can make row or column as much as you want it.

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k_90

Joined: 25 Jan 2006
Posts: 121
Helped: 18
Location: Scotland,GB

03 Mar 2008 0:10 guard ring basics

ok Visualise this.

You can draw an n-well guard at minimum widths which would give you a degree of isolation. There are a couple of things the layout engineer can do to isolate noise.

One is spacing, get as much spacing between a quiet module and a noisy one.

The next is width, the wider the nwell guard ring can be the deeper and wider the nwell will be forcing any noise deep into the substrate which has a high resistance. Look at the basics, how much easier is it to cross a stream than it is to cross a river?

Make the guard ring is far away and as wide as the die will allow remember there will always be a cost either in die area or performance find the right balance.

I place minimum guard rings around every major module and concider the full floorplan when at the first phase of a project and we've never had a problem.

varma_cs012

Joined: 22 Jan 2008
Posts: 87
Helped: 7
Location: Hyderabad

04 Mar 2008 10:06 how do i build a guard ring

Yup, As per K_90 it's the layout engineer duty to balance the cost, yield and working.

Adding to K_90 concept I want to add some more in regards of noise seperation b/w blocks.

If your technology/project allows you to use triple well process, I suggest to use the Deep_Nwell layer for complete isolation.

If we dicuss about guardring concept, What actually guarding is doing.

When ever we are forming a guardring, we are giving a negative supply to that.
i.e For Nwell guardring AVDD and P-Guardring AVSS. It means we are making that one reverse bias and forming a barrier b/w two blocks.

So as per K_90's stream and river example it's always prefred to use more widths for better noise isolation. But remember If you are increasing widhts also you are making a barrier from sidewalls only. If you see it from cross-sectional view you will get it . Still you are not completely isolating your block with noise one. Because your noise coming from substrate deeps. This is concept for N-mos devices only.

To do complete isolation, In some of my previous projects I used DEEP_NWELL as burried layer. It's possible when our technology/project allows us only. Very Happy

If any doubts regarding Burried layer...Welcome. I can give you some ans...!!! Very Happy

samajit123

Joined: 30 Aug 2007
Posts: 13

10 Mar 2008 13:54 nmos deep_nwell

Very Good Information. Thankx

Very Useful....

alecsander

Joined: 07 Jun 2007
Posts: 28

10 Mar 2008 13:54 Re: guard rings documentation

Hi all! Thanks for the replies, really helped me with some ideas.
I still have 2 questions:
- the guard ring surrounding the cell must be as close as possible to the cell, or at some distance?
- do you know some documents with real experiments of guard rings? I mean results of test chips with wide or narrow rings, close or far away rings, and others?
This would really be helpfull, to see how the silicon actually reacts.

Thanks! Very Happy

k_90

Joined: 25 Jan 2006
Posts: 121
Helped: 18
Location: Scotland,GB

10 Mar 2008 14:12 Re: guard rings documentation

1.- the guard ring surrounding the cell must be as close as possible to the cell, or at some distance?

Keep at minimum design rule spacings.

2.- do you know some documents with real experiments of guard rings? I mean results of test chips with wide or narrow rings, close or far away rings, and others?
This would really be helpfull, to see how the silicon actually reacts.

I have a pdf @ home i'll post from phillips semi. Showing an actual physical experiment. I'll dig it out!