error during synthesize VHDL code in xilinx

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gani

Joined: 26 Sep 2007
Posts: 16

16 Feb 2008 20:14 to_unsigned

hi all
can anybody help me out with this code..
i generated the below code using matlab..i'm able to simulate this code using modelsim...but when i'm trying synthesizing the same code using xilinx its giving some errors....or can anyone plz convert this code to verilog...

thanx in advance

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;

ENTITY poly_int IS
PORT( clk : IN std_logic;
clk_enable : IN std_logic;
reset : IN std_logic;
filter_in : IN real; -- double
filter_out : OUT real; -- double
ce_out : OUT std_logic
);

END poly_int;

ARCHITECTURE rtl OF poly_int IS
-- Local Functions
-- Type Definitions
TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF real; -- double
-- Constants
CONSTANT coeffphase1_1 : real := 2.5000000000000000E-001; -- double
CONSTANT coeffphase1_2 : real := 7.5000000000000000E-001; -- double
CONSTANT coeffphase2_1 : real := 5.0000000000000000E-001; -- double
CONSTANT coeffphase2_2 : real := 5.0000000000000000E-001; -- double
CONSTANT coeffphase3_1 : real := 7.5000000000000000E-001; -- double
CONSTANT coeffphase3_2 : real := 2.5000000000000000E-001; -- double
CONSTANT coeffphase4_1 : real := 1.0000000000000000E+000; -- double
CONSTANT coeffphase4_2 : real := 0.0000000000000000E+000; -- double
-- Signals
SIGNAL cur_count : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL phase_3 : std_logic; -- boolean
SIGNAL ce_out_reg : std_logic; -- boolean
SIGNAL delay_pipeline : delay_pipeline_type(0 TO 1) := (0.0, 0.0); -- double
SIGNAL product : real := 0.0; -- double
SIGNAL product_mux : real := 0.0; -- double
SIGNAL product_1 : real := 0.0; -- double
SIGNAL product_mux_1 : real := 0.0; -- double
SIGNAL sum1 : real := 0.0; -- double
SIGNAL output_register : real := 0.0; -- double

BEGIN

ce_output : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
cur_count <= to_unsigned(0, 2);
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
IF cur_count = to_unsigned(3, 2) THEN
cur_count <= to_unsigned(0, 2);
ELSE
cur_count <= cur_count + 1;
END IF;
END IF;
END IF;
END PROCESS ce_output;

phase_3 <= '1' WHEN cur_count = to_unsigned(3, 2) AND clk_enable = '1' ELSE '0';

-- ------------------ CE Output Register ------------------

ce_output_register : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
ce_out_reg <= '0';
ELSIF clk'event AND clk = '1' THEN
ce_out_reg <= phase_3;

END IF;
END PROCESS ce_output_register;

-- ---------------- Delay Registers ----------------

Delay_Pipeline_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
delay_pipeline(0 TO 1) <= (OTHERS => 0.0000000000000000E+000);
ELSIF clk'event AND clk = '1' THEN
IF phase_3 = '1' THEN
delay_pipeline(0) <= filter_in;
delay_pipeline(1) <= delay_pipeline(0);
END IF;
END IF;
END PROCESS Delay_Pipeline_process;

product_mux <= coeffphase1_2 WHEN ( cur_count=to_unsigned(0, 2) ) ELSE
coeffphase2_2 WHEN ( cur_count=to_unsigned(1, 2) ) ELSE
coeffphase3_2 WHEN ( cur_count=to_unsigned(2, 2) ) ELSE
coeffphase4_2;
product <= delay_pipeline(1) * product_mux;

product_mux_1 <= coeffphase1_1 WHEN ( cur_count=to_unsigned(0, 2) ) ELSE
coeffphase2_1 WHEN ( cur_count=to_unsigned(1, 2) ) ELSE
coeffphase3_1 WHEN ( cur_count=to_unsigned(2, 2) ) ELSE
coeffphase4_1;
product_1 <= delay_pipeline(0) * product_mux_1;

sum1 <= product_1 + product;

Output_Register_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
output_register <= 0.0000000000000000E+000;
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
output_register <= sum1;
END IF;
END IF;
END PROCESS Output_Register_process;

-- Assignment Statements
ce_out <= ce_out_reg;
filter_out <= output_register;
END rtl;

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

16 Feb 2008 20:58 to_unsigned vhdl

I'll bet the error message was something like, ". . . Signal <filter_in> of type real is not supported."

Your code contains "real" (floating-point) data type, which isn't supported by Xilinx XST, the HDL synthesizer. That's a common limitation of today's HDL synthesis tools.

Try modifying your MATLAB project so it generates integer or fixed-point arithmetic.

gani

Joined: 26 Sep 2007
Posts: 16

17 Feb 2008 9:33 vhdl code for xilinx

thank you for ur reply....
yes that is true..i'm got the same error as you mentioned..i tried changing ieee standards now i'm facing problem with to_unsigned..is there any libraries for to_unsigned in hdl....

and i generated even verilog code using matlab..can i synthesize $bitstoreal in xilinx???? i've already changed my code using fixed point...but i want to synthesize the same code using xilinx if there is no such option i'll continue with fixed point only...

FvM

Joined: 22 Jan 2008
Posts: 5160
Helped: 767
Location: Bochum, Germany

17 Feb 2008 11:01 floating point unit vhdl code for xilinx

Hello,

the conversion functions provided in ieee.std_logic_arith are UNSIGNED(x) for bitvector to unsigned "type casting" and CONV_UNSIGNED(x,length) for integer to unsigned conversion, similar with SIGNED type.

Verilog $bitstoreal ends up in the same issue as discussed. It's useless without a real data type in synthesizable code. However, some IP for real arithmetic is available (don't know particularly with Xilinx), but it uses bitvectors at the interface. Porting matlab code to use such IP (e.g. float multipliers) would imply specialized conversion functions. Thus it's a good idea to make matlab design the fixed point aritmetics as suggested.

Regards,
Frank

rsrinivas

Joined: 10 Oct 2006
Posts: 419
Helped: 36
Location: bengalooru

18 Feb 2008 11:39 to_unsigned with two arguments vhdl

U havent quantized ur design in Matlab
check the filter design user guide
after u design a filter u have to quantize it to fixed point so tat u can genrate ur synthesizable HDL.

Regards

nxtech

Joined: 13 Jun 2007
Posts: 257
Helped: 15
Location: Watching You!

18 Feb 2008 14:55 steps to synthesize a vhdl code in xilinx

Just one more point to add, converting your code to Verilog wont help you either. You will still have the issue of floating point numbers to deal with.

E

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18 Feb 2008 14:55 Ads

mmetre

Joined: 16 May 2008
Posts: 1

16 May 2008 10:31 xilinx + real

HI gani, this is M & M HRU?
I m requesting to u plz tell me a procedure how to convert matlab code to VHDL code, becoz i written matlab code but i want to convert that to VHDL code. So kindly i request u plz reply me with astep by step procedure for conversion of VHDL code. so i m waiting for ur reply, advance thanking u.

Regards
M & M