Successive Approximation ADC

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firsttimedesigning

Joined: 04 Jul 2007
Posts: 98

06 Feb 2008 2:43 verilog code for sar

So I am desingning a SA ADC. The problem I am having is that how can I design the Successive Approximation Register (SAR). Do I design it using state diagrams?
If I use state diagrams (Moore State) to design it, then I will have to draw A LOT state diagrams for a SA ADC that can convert 8 bits. State diagrams is the only way that I know, is there any other way?

mahgoub

Joined: 26 Oct 2007
Posts: 94
Helped: 2

06 Feb 2008 8:28 successive approximation adc

you can use an old implemention

Added after 11 minutes:

try data converter book there are many in forum

arsenal

Joined: 17 Oct 2004
Posts: 136
Helped: 11

07 Feb 2008 23:53 sar adc basics

Refer to Allen's book, in the charpter of ADC, there is a perfect diagram of SAR ADC, just do as that diagram!

mahgoub

Joined: 26 Oct 2007
Posts: 94
Helped: 2

09 Feb 2008 23:17 sucessive approximation

do you hAVE ALInk to it arsenal

fredflinstone

Joined: 20 May 2005
Posts: 75
Helped: 17
Location: Bangalore, India

15 Feb 2008 5:11 sar verilog code

SA register can be made as a simple shift register which shifts a logic HIGH from MSB flop to LSB flop. Also it stores the current comparator input to the corresponding flop.
This should be very easy to implement.. either writing VHDL code or manual design...

wateror

Joined: 26 Aug 2007
Posts: 81

18 Feb 2008 4:36 sa successiv approximation

allen's book for a start

Tipu

Joined: 12 Sep 2007
Posts: 21
Location: INDIA (HYDERABAD)

19 Feb 2008 17:27 successive approximation register verilog code

Hai

i had wriiten a code in verilog? but for better accuracy i think i need to go for analog design do u think may i right?

fredflinstone

Joined: 20 May 2005
Posts: 75
Helped: 17
Location: Bangalore, India

24 Feb 2008 14:12 state machine+successive

The Successive Approximation Register can be designed entirely in digital ... no need to do anything in analog..

arjun_p_cet

Joined: 27 Feb 2007
Posts: 10

24 Feb 2008 17:09 sar adc book

this book from analog devices will help u with the basics

h**p://rapidshare.com/files/53248394/3-09091.zip
(dont forget to put 't' in place of '*')

Added after 36 minutes:

also check these books....

Analog Circuit Design: High-Speed A-D Converters,

http://mihd.net/s9rqgj

Added after 12 minutes:

Data Converters

http://rapidshare.com/files/58078383/DC.rar

pass:gigapedia.org

ashish_chauhan

Joined: 02 Sep 2007
Posts: 262
Helped: 39

25 Feb 2008 11:15 analog circuit design plassche rapidshare

the password does not work... seems u have changed it...?

endrawan

Joined: 27 Feb 2008
Posts: 3

27 Feb 2008 4:13 successive approximation adc converter

It can be disgned first in P-Spice

ee07d003

Joined: 18 Feb 2008
Posts: 24
Helped: 2

27 Feb 2008 14:17 sar verilog program

Hey, you get videos on web teaching SAR-ADC design. In fact, Maxim-ic, National Semiconductor and Analog Devices provide application notes on SAR-ADC.

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27 Feb 2008 14:17 Ads

raj_shekar

Joined: 27 Feb 2008
Posts: 11

28 Feb 2008 5:17 sar verilog program

There is no need for state machine if u know about how many cycles conversion takes place. u can generate the sample signal by delay elements(F/Fs) and use shift registers to transfer 1 from MSB F/F to other F/F for every conversion cycle. and latch the compartor output by generating the latch clock.

neter

Joined: 15 Jul 2004
Posts: 50

04 Mar 2008 8:38 sar verilog code

Have any design example for SAR ADC?

mahgoub

Joined: 26 Oct 2007
Posts: 94
Helped: 2

06 Mar 2008 16:46 sar code in verilog

search im this site

arjun_p_cet

Joined: 27 Feb 2007
Posts: 10

08 Mar 2008 13:11 sar adc verilog code

try "CMOS Analog to digital and Digital to Analog converters" by Rud van Plassche.....u get basic ideas...also u get information about good reference papers on SA ADCs

MikeR

Joined: 16 Dec 2006
Posts: 79
Helped: 6
Location: Belarus

28 Mar 2008 12:55 sar adcs basics

When I design ADC (any type) for algoritm or logic I use verilog code. And for SAR you mast have not only 1 reg. Your logic bloc must contain driver for S/H, driver for Comparator and DAC. Realize this functions in primitive logic components not use VERILOG is difficult.