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ISE vs qu(at)rtus
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mharries



Joined: 30 Jan 2008
Posts: 3
Post01 Feb 2008 8:48   

ISE vs qu(at)rtus
i'm a qu(at)rtus user. Recently, i have to use xilinx tool to synthesize and simulate. but, i'm really confused because there's a lot of thing i didn't know about xilinx tools.
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FvM



Joined: 22 Jan 2008
Posts: 5151
Helped: 766
Location: Bochum, Germany
Post01 Feb 2008 10:09   

Re: ISE vs qu(at)rtus
Hello,

as a general difference, Xlilinx ISE has been assembled from several OEM tools, the same e. g. with Lattice. Thus operation isn't as covenient as you're probably used to with qu(at)rtus. But don't panic! It's basically understandable, they have help files, examples, tutorials and such. As far as no particular device resources are involved, you can also perform HDL syntax check and functional simulation in qu(at)rtus.

Regards,
Frank
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cj007



Joined: 31 Jan 2008
Posts: 18
Location: Singapore
Post01 Feb 2008 13:15   

Re: ISE vs qu(at)rtus
XIlinx is a powerful FPGA Design tool if compare to ALTERA. If you're expert/advanced FPGA designer, most probably you wil think Xilinx is no.1 compare to ALTERA because you have more control on your design and PlanAhead is actually a good Place & Route tool where it provide the best routing for you if you master it...


I vote Xilinx No.1 in FPGA design market...
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mharries



Joined: 30 Jan 2008
Posts: 3
Post01 Feb 2008 13:48   

ISE vs qu(at)rtus
i'm agree with you cj007 and technically, i'm not an expert user. i just familiar with qu(at)rtus.. do you familiar with xilinx tools? can you help me?
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Post01 Feb 2008 13:48   

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Iouri



Joined: 17 Aug 2005
Posts: 687
Helped: 79
Post01 Feb 2008 19:12   

ISE vs qu(at)rtus
qu(at)rtus syntheize tool is giving very close result as Synplicity

Altera design constrain using *.SDC format (which is standard de-facto in ASIC industry) which means when you constraining your FPGA you taken trace delays on PCB in consideration, not like Xilinx when you have take timing report and incorporated in PCB

from code changes to FPGA only two mouse clicks in Altera, Xilinx way more
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