need help on rail to rail op

EDAboard.com Forum Index -> Analog Circuit Design -> need help on rail to rail op

Author

Message

zxasqw123

Joined: 02 Apr 2007
Posts: 47

22 Jan 2008 10:32 need help on rail to rail op

i have designed a rail to rail op for LCD driver,i use the floating CLASS AB output stage ,but to my surprise ,the voltage between gate of NMOS/PMOS is not followed .so when i charge the cap ,|VGS|(PMOS) increase ,at the same time VGS (NMOS) is also increasing ,and when i discharge the cap,|VGS|(NMOS) is increasing,at the same time |VGS|(PMOS) is also increaing ,i am really confused ,why my floating CLASS AB can not work as a battery ,can anyone give me some advice ?
thanks in advance.

Google
AdSense
Google Adsense

22 Jan 2008 10:32 Ads

zxasqw123

Joined: 02 Apr 2007
Posts: 47

23 Jan 2008 7:26 Re: need help on rail to rail op

maybe my question is not clear enough,let me depict the question specificly.
as is show in the picture ,when i charge the cap (VOUT change form 0 to VDD)
my gatep is decreasing ,at the same time the gaten is increaing ,then there is a current path from pp14 to np4 and there is power loss .and when discharge the cap ,the same thing happens.i am really confused why gatep and gaten can not work as a battery?
why not gatep is increasing ,when gaten is increasing ?
i am looking forward everyone 's help
thanks in advance