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firsttimedesigning
Joined: 04 Jul 2007
Posts: 97
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 16 Jan 2008 2:51 switch capacitor integrator |
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so i have designed a switch capacitor integrator (please see file switch-cap integrator). unforturnately, the result looks very weird. (please see file sc-output)
but if i replace the opamp with an ideal opamp, then the result becomes correct. (please see file sc-output(idealopamp)).
So i believe the problem is casued by the opamp that i have designed. But how can i make my opamp better so that the result looks like that of the ideal one?
The opamp that i designed has high gain(about 80dB) and high bandwidth(1Ghz). What else can i do?
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Old Nick
Joined: 14 Sep 2007
Posts: 370
Helped: 43
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| 16 Jan 2008 3:52 Re: switch capacitor integrator |
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Looks like switching noise to me, exactly as I'd expect.
Kill the switches before you read and it'll be fine.
I've built several SC integerators on chip, (different architecture and useage) and I would expect to see that with small capacitances (my capacitances were tied to ground), the noise decreased as the size of the ap increased. But you just kill the clocks when you read out. If you zoom in on the wave form, I bet you'll see that the spikes are quite narrow, and the output is actually at the expected value for 80-90% of the clock period
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firsttimedesigning
Joined: 04 Jul 2007
Posts: 97
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| 16 Jan 2008 4:06 Re: switch capacitor integrator |
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Kill the switches?
but if take out the switches, then it wont be "switch" capacitor, which is not what i want...yes, indeed, the spikes are narrow and i have no idea how to get rid of them...
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chungming
Joined: 23 Mar 2006
Posts: 94
Helped: 7
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| 16 Jan 2008 11:39 Re: switch capacitor integrator |
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Enlarge the switch NMOS width W, and gate voltage if possible.
But the sampling cap is so small ,larger W may contribute large charge injection....
So i think there has trade-off between then.
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jiangxb
Joined: 01 Apr 2007
Posts: 280
Helped: 20
Location: hangzhou, china
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| 16 Jan 2008 11:54 Re: switch capacitor integrator |
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| maybe because the on-resistance of switch is large, it corrupts the integrator frequency response in integration phase. you can increase the switch width and its gate control voltage to reduce its on-resistance and try it again.
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Old Nick
Joined: 14 Sep 2007
Posts: 370
Helped: 43
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| 16 Jan 2008 13:14 Re: switch capacitor integrator |
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| firsttimedesigning wrote: |
Kill the switches?
but if take out the switches, then it wont be "switch" capacitor, which is not what i want...yes, indeed, the spikes are narrow and i have no idea how to get rid of them... |
Yes, but not forever!
It will be an integrator before you kill the switches and it will be an integrator when you turn them back on. All your doing is making sure there is no spike whilst youre reading the value.
But this is most suitable if you are integrating over a set period and want to read the value at the end.
You can try and make things bigger to minimise the effect as I said, but it is largely cosmetic. as long as you're not sampling and holding the top of a peak.
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linkfox
Joined: 18 Dec 2007
Posts: 44
Helped: 2
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| 16 Jan 2008 21:08 switch capacitor integrator |
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one improvement can be replace all the NMOS switches with Transmission Gates,
make the nmos/pmos in the TG to be the same size to reduce the charge injection.
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firsttimedesigning
Joined: 04 Jul 2007
Posts: 97
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| 17 Jan 2008 1:05 Re: switch capacitor integrator |
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To Nick,
Thx for the reply, Yeah I can see how that works. Read in the value after i kill the switches. But is there anyway to get rid of the spikes? or rather to decrease the magnitude of the spikes? Make the graph looks like the one that uses ideal op-amp
To Fox,
Thx for the reply, i have tried TG and dummy switches but neither one of them can get rid of the spikes....
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xdy83
Joined: 12 May 2007
Posts: 14
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| 19 Jan 2008 5:18 switch capacitor integrator |
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u should change a bigger sample cap, and try again.
maybe the problem comes from your op , i think.
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pavan_adc
Joined: 30 Dec 2007
Posts: 2
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| 22 Jan 2008 13:31 Re: switch capacitor integrator |
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me also got the same problem when designing the switched cap int.
i think the problem is with switches only. i have used the tr gates with large width then also i am getting very small spikes but it reduces compared to nmos switches.
how to reduce it completely.
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newtoanalogdesign
Joined: 25 Jan 2008
Posts: 3
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| 25 Jan 2008 6:39 Re: switch capacitor integrator |
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me also getting same problem
can we increase the gate voltage(in this case clock) above the supply voltage.
i am using 3.3v supply and the clock voltage of 3.3v . can i increase it beyond 3.3v
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mickey_melomane
Joined: 16 Jun 2006
Posts: 45
Helped: 2
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| 25 Jan 2008 13:36 switch capacitor integrator |
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In switches, increasing W/L reduces the ON resistance, but the increased Cgs, contributes to the feedthrough that u see at the output. U may use bottom plate sampling techniques to minimize it.
Added after 1 minutes:
NMOS switch produces a negative error after injection, and PMOS produces a positive error. Proper sizing of the two in a transmission gate may help u nullify the injection voltages. But note that this canceling of injection voltages happens only for one value of Vin..
Added after 2 minutes:
When source node (input node) of a switch increases, the effective gate -source voltage decreases, and the switch may turn OFF. To combat this effect, gate is made to increase even above Vdd !!! Refer the paper by Abo and Gray, "10 bit 14.3 MSPS pipelined ADC". This ll explain the clock boosting scheme...
Sidharth
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arsenal
Joined: 17 Oct 2004
Posts: 134
Helped: 11
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| 26 Jan 2008 2:39 switch capacitor integrator |
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| decrease size of the switches, reduce the gain of the opamp a little bit
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umery2k75
Joined: 19 Apr 2006
Posts: 236
Helped: 19
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| 26 Jan 2008 5:02 Re: switch capacitor integrator |
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Switch capacitor integrator term is new to me, I read it first time 
I read about it was something like few couple of switches and a capacitor are used to simulate a resistor, but why do we want to make artifical type of resistor, why don't we add a real resistor?
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edajason
Joined: 05 Nov 2004
Posts: 59
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| 08 Feb 2008 23:17 switch capacitor integrator |
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1) Try to use a large R (not affect your BW) shunting with your feedback Cap if you use the real opamp. re-run the simulation to see what's the difference.
2) For your clock stimulus, make sure you are using 2 phase non-overlapping clocks. The non-overlapping period could be roughly 1-5% of the high level period.
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lladnar23
Joined: 20 Mar 2006
Posts: 200
Helped: 27
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| 09 Feb 2008 4:47 switch capacitor integrator |
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| Since this is a sampled-data circuit, like Nick said, those switching transients don't matter a great deal. The useful data is in the voltage level between the clock spikes. Your ADC will sample the voltage and won't see the spikes. If you are going to use the output in a continuous system, you'd need to run it through a lowpass filter anyway to wipe out the frequency content past Nyquist...
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sm_rashtyan
Joined: 11 Feb 2008
Posts: 3
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| 20 Feb 2008 18:23 switch capacitor integrator |
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hi
I think If you change circuit to differantial mode,all of problem caused by charge injection and clock feedthrough are solved. in the other word in differential mode the effect of clock feedthrough is completly canceled and the effect of charge injection is decreased significantly. however if you decresed the sampeling frequency to about 50khz the behaviour of circuit will be better due to decerement of charge injection and clock feed through
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dkace
Joined: 14 Jun 2002
Posts: 356
Helped: 24
Location: Greece
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| 21 Feb 2008 16:16 Re: switch capacitor integrator |
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Hi,
I will be a bit extensive on this as I made a patent on a SC ADC and I studied all the above.
You need to build an integrator : First sample the input then through it to the output . I will use it as follows: So M5-M2, M3-M6 should work together securing a sample and hold scheme.
Then, let's see main problems of this topology:
1. Clock Feedthrough,
2. Switch glitches,
3. Opamp Offset
4. Capacitor mismatch.
Then, an opamp should be a two stage OTA with high current drive on the output in order to avoid delays and erronius output due to slow charging etc.
1.Clock feedthrough and part of the glithing problems can indeed be corrected with a fully differential OPAMP.
2.Glitches will definite be away if you use dummy switches of equal size on the two sides of each switch, controlled by the complementary clock that controls the main switch. This will result in giving the remaining charges an equal path to both directions and negate part of the glitching. The Transmission gate will take care the rest.
3.Opamp offset is a tricky one. It "seats" there on start up and you can avoid it. But you can hide it! Sample the opamp input on a capacitor right before the input on its inergrator sampling ( when M5-M2 are on). This is the auto zero technique.The other plate of the capacitor will be connected via a switch to the ground or the common voltage ( in case of a differential topology). Then when
the input will be applied there the offset voltage of teh opamp will have allready been negated by the charged capacitor. This will be happening on every sampling. Offset is off!
4. Capacitor mismatch is the hardest thing to avoid. That's why I have a patent on it (he,he)! If it is just for schematic you need to take no further measures.
I hope I helped a bit,
D.
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xdy83
Joined: 12 May 2007
Posts: 14
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| 09 Mar 2008 17:49 Re: switch capacitor integrator |
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i think the problem comes from the op. maybe the input Vcm is not right, it can be
zero ? bcos, the ideal op is all right.
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alonemrt
Joined: 09 Mar 2008
Posts: 10
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| 11 Mar 2008 11:41 Re: switch capacitor integrator |
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| i think the problem comes from the opamp
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tanuki
Joined: 11 Jun 2001
Posts: 80
Helped: 2
Location: Spain
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| 11 Mar 2008 17:33 Re: switch capacitor integrator |
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I think you need to change your gate signals. M5 and M6 share the same gate signal and M2 and M3. During switching both of these pairs will conduct at the same time ("cross-conduct", "shoot through", etc.). Setup the phase clocks so there there is no overlap (suggestion: buffer using a SR flip flop, made of cross coupled nor gates.).
Also the opamp needs to be fast enough to reset the "-" node to zero (virtual ground) well before the next phase starts. On the other side of speed, you might also put a resistor in series with the opamp output to limit the charge transfer current current, so that the opamp doesn't go into short circuit limiting. In an actual circuit, the opamp voltages sources will have some impedance, therefore decouple the supply carefully and added ferrite beads, etc. You want to adjust the current limiting resistor so that on the largest input the opamp just manages to reset the "-" node to 99% (or as you like) just as the transfer phase ends.
Once you get the basic circuit working ... add in the parasitic elements too ... considering these elements is where your design skills will improve most. 
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xdy83
Joined: 12 May 2007
Posts: 14
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| 22 Mar 2008 15:40 Re: switch capacitor integrator |
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2) For your clock stimulus, make sure you are using 2 phase non-overlapping clocks.
this is the point
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lovexxnu
Joined: 14 Dec 2007
Posts: 13
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| 22 Mar 2008 17:05 Re: switch capacitor integrator |
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the key is the clock and switches, I think
non-overlapped clock must be assured, and transit gate should be applied.
ideal op means the input impedance is infinite, but real is not.
so some of the real effects will not appear in ideal op.
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icehot
Joined: 09 Apr 2008
Posts: 2
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| 09 Apr 2008 13:45 switch capacitor integrator |
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Agree with dkace except that:
"2.Glitches will definite be away if you use dummy switches of equal size on the two sides of each switch"
I think the dummy switches have to be the half size of the two sides of each switch.
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yezeg
Joined: 12 Jan 2006
Posts: 15
Helped: 1
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| 26 Apr 2008 15:11 switch capacitor integrator |
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The ideal opa is work well.I thinK the proble is OPA but not the switch or capacitor .
Tell us the frequency if switch and the OPA's gainband and settingtime!
Maybe the opa is not satable ,what is the PM?
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