For new testbench, VERA, Specman/E, or Systemverilog?

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boardlanguage

Joined: 06 Apr 2007
Posts: 96
Helped: 4

10 Jan 2008 23:19 system verilog vs specman

I think we all know Systemverilog is here to stay, since it's a convergence HDL language (Design and Verification, as opposed to Verification only), unlike E or VERA.

But I've never used VERA or E. And as the old saying goes, "Jack of all trades == master of none!" In other words, a specialized verification language E/VERA will perform verification better than a general-purpose language like Systemverilog.

For testbench and verification, can someone tell me what advantages VERA and E have, compared to Systemverilog? Is there anything (testbench/verification wise) Systemverilog does better than VERA or E?

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mssajwan

Joined: 19 May 2006
Posts: 103
Helped: 10
Location: Banaglore

11 Jan 2008 6:29 specman testbench

Hi,
No I don't think there are much differences in these languages from Verification perspective.
If you see from past even you can do the verification using Verilog as well.
Now the question is where SystemVerilog is ahead , & it is thats why all 3 major eda vendors are supporting SV. its a IEEE standard. U dont need to buy spearte simulator as woith E or Vera.
Vera is specific to Synopsys and E is to cadence so the cost factor is the major factor.
So in near future we may see SystemVerilog only.
So just work with any language u get opportunity to work with
-Manmohan

salma ali bakr

Joined: 27 Jan 2006
Posts: 973
Helped: 80

11 Jan 2008 9:55 vera vs systemverilog

i think that one of the advantages of SV would be that you have both the design and the verification codes integrated together...no need for external files!

also, the adoption of constrained-random testbenches, functional coverage and assertions is perfectly coherent with the use of SV

Read this interesting article to know more please:

http://www.eetimes.com/showArticle.jhtml;jsessionid=LMTQROZEZBUCKQSNDLPCKHSCJUNN2JVN?articleID=197005401

aji_vlsi

Joined: 10 Sep 2004
Posts: 640
Helped: 72
Location: Bangalore, India

13 Jan 2008 17:08 specman vs system verilog

Hi,

boardlanguage wrote:

But I've never used VERA or E. And as the old saying goes, "Jack of all trades == master of none!" In other words, a specialized verification language E/VERA will perform verification better than a general-purpose language like Systemverilog.

You are correct. However one can "live" with some limitations if the broader goal of "everyone can debug everything" is achieved - to me that's the single most advantage of SystemVerilog.

Quote:

For testbench and verification, can someone tell me what advantages VERA and E have, compared to Systemverilog?

Well a detailed list will be overwhelming and meaningless. The goal of "doing verification" is doable with any of these, and for any new projects I see more and more SV being used.

One of the fundamental differences bet'n E and SV is AOP vs. OOP. There are some good papers on this topic, look at cdnusers.org. Also see:

http://www.synopsys.com/cgi-bin/systemverilog/pdfr1.cgi?file=SystemVerilog_for_e_Experts_Janick_Bergeron.pdf

Quote:

Is there anything (testbench/verification wise) Systemverilog does better than VERA or E?

Eae of use, single look and feel - does not create a barrier for Designers to debug TB and vice versa.

Cheers
Ajeetha, CVC
www.noveldv.com