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help in system verilog
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deepu_s_s



Joined: 24 Mar 2007
Posts: 329
Helped: 13
Post13 Dec 2007 14:48   

help in system verilog
hi !
i am having a doubt in sv.
consider a micro processor architceture..all the bus elated signals are defined in an interface.. all these signals are shared by different blocks like alu,cu,memory, instruction decoder etc... some of these blocks dont utilize all of the signals defined in the interface. but the unused signals cant be left open like in MODULE.

then wont be there any error. how to resolve problem?

thanks and regards
Deepak
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naveen reddy



Joined: 02 Jun 2005
Posts: 27
Post20 Dec 2007 7:06   

help in system verilog
Hi
If there are unused signals in the blocks which are declared in the interface, declare this signals as bit. These signals will be in the X state.
Hope this helps

Regards,
Naveen
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mkrishnap



Joined: 28 Nov 2007
Posts: 11
Post20 Dec 2007 8:34   

Re: help in system verilog
Deepu_s_s,

In total, the signals in the interface are connected to one or the other module & no signal is kept unconnected. Then how do you say that they left unconnected? We will be using different instances of the same interface and use the signals whichever are required for that particular module. If a signal is used nowhere, it will be deleted obviously!

The "modport" construct here will help to identify the directions even.

-mkrishnap
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