help: how to solve this xilinx translate issue?

EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> help: how to solve this xilinx translate issue?

Author

Message

simon111

Joined: 28 Jun 2007
Posts: 7
Helped: 1

08 Dec 2007 14:36 output pad net has an illegal load

hi experts:
i am new to fpga,
i am using xilinx spartan3e and want transfer some data with cypress fx2 via slave fifo interface. i work with ise,
i write a logic circuit, i can synthesize it successfully, but i can not translate it successfully

following is my code:

Code:

// ep2 -- out , wirte the image data,
// ep6 -- in , read the image data
module slave_fifo_syn(
sys_clk ,
sys_rst_n ,
usb_fifo_clk ,
usb_slwr ,
usb_slrd ,
usb_sloe ,
usb_fifo ,
usb_ad ,
usb_flaga ,
usb_flagb ,
usb_flagc ,
usb_pktend ,
usb_slcs
);
input sys_clk ; // system clk
input sys_rst_n ; // system reset, active low
input usb_flaga ; // flaga is the ep2 empty flag, active low
input usb_flagb ; // flagb is the ep6 full flag, active low
input usb_flagc ; // used
output usb_fifo_clk ; // clk for slave fifo
output usb_slwr ; // slave fifo write, active low
output usb_slrd ; // slave fifo read, active low
output usb_sloe ; // slave fifo output enable, active low
output usb_slcs ; // slave fifo chip select, active low
inout [ 7:0 ] usb_fifo ; // slave fifo data bus, bi-direction
output [ 1:0 ] usb_ad ; // ep fifo address, 0--ep2 2--dp6
output usb_pktend ; // packet end, active low

// code start here
// generate the usb fifo clk by dcm
dcm_66_33 dcm_inst (
.CLKIN_IN ( sys_clk )
,.RST_IN ( !sys_rst_n )
,.CLKFX_OUT ( usb_fifo_clk )
,.CLKIN_IBUFG_OUT ( )
,.CLK0_OUT ( )
,.LOCKED_OUT ( )
);
reg [ 8:0 ] x ;
reg [ 8:0 ] y ;
reg [17:0 ] waddr ;
wire [ 7:0 ] d ;
reg [ 7:0 ] dd ;
wire [14:0 ] ramaddr ;
reg usb_slrd ;
reg [ 7:0 ] cmd[1:3];
wire reading ;

wire ef ; // empyt flag
wire ff ; // full flag

assign ef = ~usb_flaga;
assign ff = ~usb_flagb;
assign reading = (cmd[1]==8'h01) & (cmd[2]==8'h02) & (|cmd[3]); // reading

// flagb is ep6 full flag, ep6 is a auto in endpoint
// flaga is ep2 empty flag, ep6 is a auto out endpoint

assign usb_slwr = ~usb_slrd | ff ;
assign usb_fifo = usb_flaga?d:8'bz ;
assign usb_sloe = usb_slrd ;
assign usb_ad = usb_slrd?2'h2:2'h0 ;
assign usb_pktend = 1'h1 ;
assign usb_cs = 1'h0 ;
assign ramaddr = usb_slrd?{y[6:0],x[7:0]}:waddr ;

always @(posedge usb_fifo_clk or negedge sys_rst_n)
begin
if(~sys_rst_n)
begin
x<= #1 8'h0;
y<= #1 8'h0;
cmd[1] <= #1 8'h00 ;
cmd[2] <= #1 8'h00 ;
cmd[3] <= #1 8'h00 ;
waddr <= #1 15'h00 ;
end
else
begin
dd <= #1 d;
usb_slrd <= #1 ef;
if(~usb_slrd)
begin
if(~reading)
begin
cmd[3] <= #1 usb_fifo;
cmd[2] <= #1 cmd[3] ;
cmd[1] <= #1 cmd[2] ;
end
else
begin
waddr <= #1 waddr+15'h01;
cmd[3] <= #1 cmd[3]-8'h01;
end
end
else if(~usb_slwr)
begin
x<=#1 x+8'h01;
if(&x)
y<=#1 y+8'h01;
end
end
end
// this ram store a image,
// cypress fx2 can read/write this image
imgram ram (
.addr ( ramaddr )
,.clk ( usb_fifo_clk )
,.din ( usb_fifo )
,.dout ( d )
,.we ( reading )
);
endmodule

and this is error message ise report.

Quote:

ERROR:NgdBuild:809 - output pad net 'usb_fifo<7>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'usb_fifo<6>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'usb_fifo<5>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'usb_fifo<4>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'usb_fifo<3>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'usb_fifo<2>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'usb_fifo<1>' has an illegal load:
ERROR:NgdBuild:809 - output pad net 'usb_fifo<0>' has an illegal load:

how can i do? i have no idea

thank you in advance

Simon

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

08 Dec 2007 16:31 error:ngdbuild:809

I haven't seen that error message before. Do you get any other related warning messages?
Modules dcm_66_33 and imgram are missing, so I can't try building the project to reproduce the error.

What is usb_fifo connected to outside of module slave_fifo_syn?
Is slave_fifo_syn your top level module?
How is usb_fifo declared in module imgram?

simon111

Joined: 28 Jun 2007
Posts: 7
Helped: 1

09 Dec 2007 2:59 ngdbuild:809

hi echo47
very appreciate you help !

echo47 wrote:

I haven't seen that error message before. Do you get any other related warning messages?

in the synthesize process, i get a warning:
WARNING:Xst:2183 - Unit slave_fifo_syn: the following tristate(s) are NOT replaced by logic (Please refer to Answer Record 20048 for more information): usb_fifo<0>, usb_fifo<1>, usb_fifo<2>, usb_fifo<3>, usb_fifo<4>, usb_fifo<5>, usb_fifo<6>, usb_fifo<7>.
what the message mean?
i can not use spartan3e?

echo47 wrote:

Modules dcm_66_33 and imgram are missing, so I can't try building the project to reproduce the error.

i give you the full project, see the attachment
in my projects,
almigphty is the top level module,
led_con control 2 leds, the 2 leds are active low, this module is work
slave_fifo_syn implements a salve fifo synchro interface, it communicates with cypress fx2 chip, the fpga is master, the fx2 chip is slave
dcm_66_33 is a DCM_SP core, my sys_clk is 66M, i want get a 33M clock to driver usb_fifo_clk
imgram is a single port ram core, store some date. i want fx2 chip can write/read these data via salve fifo interface
the salve fifo is 8bits mode

[quote="echo47"]
What is usb_fifo connected to outside of module slave_fifo_syn?
[\quote]
usb_fifo is a bi-direction date bus, it connects to the fd pin of the fx2 chip

[quote="echo47"]
Is slave_fifo_syn your top level module?
[\quote]
no, in project, the almigphty is

[quote="echo47"]
How is usb_fifo declared in module imgram?
[\quote]
imgram is single port ram core,
addr is the address signal
clk is the clock
din is the input date bus
dout is the output date bus
we is the write enable singal, active high

thank you again
have a great day
Simon

Sorry, but you need login in to view this attachment

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

09 Dec 2007 7:24 ngdbuild:809 - output pad net has lillegal load

I can now easily reproduce the problem in ISE 9.2.03i. I see two simple but fatal typo errors:
1. In almighty.v, change usb_fifo from output to inout.
2. In almighty.ucf, change LVCOMS33 to LVCMOS33.

The project now builds and routes without errors, and generates three-state I/O pins for usb_fifo.
I see a few other warnings messages, so check them out.
Good luck!