dual clock counter

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anoop12

Joined: 29 Nov 2006
Posts: 69
Helped: 1

15 Nov 2007 7:17 dual clock counter

Hi all,
I need vhdl code for counter 74192( dual clock synchronous ).
I have written the code as below.
When I simulate it for upcounting or downcounting individually i.e. with only one process at a time, it works fine. But with two processes at a time it gives no output .
can anyone correct it?
here is the code
----------------------------------------------------------------------------------------
-- TI_UD_192.vhd

-- IC 74192 Decade Counter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
------------------------------------------------------------------------------------------------------------------------------------------------------------
entity DECADE_COUNTER is
port ( I_P: in std_logic_vector(3 downto 0); -- input
I_UP:in std_logic; -- up-counting clock
I_DOWN: in std_logic; -- down-counting clock
I_CLR: in std_logic; -- Asynchronous Clear
I_load_N:in std_logic; --load to BCD 7,active low(Preset)
O_Q: out std_logic_vector(3 downto 0); -- output
O_B_N: out std_logic; - down counting borrow pulse
O_C_N: out std_logic); - up counting carry pulse
end DECADE_COUNTER;

--------------------------------------------------------------------------------------------------------------------------------------------------------------
architecture BEHAV of DECADE_COUNTER is
signal COUNT:std_logic_vector(3 downto 0);
begin
-- process for up counting
----------------------------------------------------------------------------------------------------------------------------------------------------------------
process(I_UP,I_CLR)
begin
if (I_CLR='1') then count<="0000";
elsif ( I_UP'event and I_UP='1') then
if(I_LOAD_N='0') then count<=I_P;
else count<=count + 1;
end if;
if (count="1001") then count<="0000";
end if;
end if;

end process;
-------------------------------------------------------------------------------------------------------------------------------------------------------------------
O_C_N<='0' when count="1001" else'1';

--process for down counting
------------------------------------------------------------------------------------------------------------------------------------------------------------------
process(I_DOWN,I_CLR)
begin
if (I_CLR='1') then count<="0000";
elsif ( I_DOWN'event and I_DOWN='1') then
if(I_LOAD_N='0') then count<=I_P;
count<=count-1;
end if;
if (count="0000") then count<="1001";
end if;
end if;

end process;
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
O_B_N<='0' when count="0000" else'1';

------------------------------------------------------------------------------------------------------------------------------------------------------------------------

O_Q<= count ;
end BEHAV;
--------------------------

aajizattari

Joined: 13 Nov 2007
Posts: 56
Helped: 8

15 Nov 2007 11:13 dual clock counter

Hey man !!! I am not that familiar with VHDL

but

I tell u one thing ..... Dont use one variable or signal as a target in two processes

U better count up and down in a sigle processs using IF ELSE Structure

Hope that Helps U !!!!!!!

If so DO GET ME few Points on this forum !!!

I have begun to study VHDL may be I can answer u better a feww days later

master_picengineer

Joined: 03 Sep 2007
Posts: 1050
Helped: 62

15 Nov 2007 12:57 dual clock counter

You can't use 2 process since they assign a value for the same variable "count".
This is permitted in VHDL:
A process can assign value to Var1, Var2, ...VarN
but:
process1 and Process2 can't assign value to Var1, that's wha you did.

addn

Joined: 08 Apr 2006
Posts: 35

15 Nov 2007 13:26 Re: dual clock counter

hi,
you can try that

add internal node
signal up_down_clk:std_logic;
signal up_down_flag:std_logic;

then
up_down_clk<=I_UP AND I_DOWN;
up_down_flag<=...............................

process(up_down_clk,I_CLR,I_LOAD_N,up_down_flag)
begin
if (I_CLR='1') then
count<="0000";
elsif(I_LOAD_N='0') then
count<=I_P;
elsif(up_down_clk'event and up_down_clk='1') then
if(up_down_flag='1') then
if(count="1001") then
count<="0000";
else
count<=count+1;
end if;
else
......................
......................
end if;
end if;
end process;

anoop12

Joined: 29 Nov 2006
Posts: 69
Helped: 1

19 Nov 2007 7:41 Re: dual clock counter

hello addn,
thanks for that wonderful suggestion.
Will you please clarify how to get that iflag signal that you have taken in your code.
regards

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19 Nov 2007 7:41 Ads

addn

Joined: 08 Apr 2006
Posts: 35

19 Nov 2007 13:44 dual clock counter

hi,
about the flag
you need two negative edge D-FF with asynchronous reset

D-FF1:D<->'1',CLK<->I_UP,/RESET<->I_DOWN

D-FF2:D<->'1',CLK<->I_DOWN,/RESET<->I_UP

and then

up_down_flag<=Q1 AND NOT Q2;