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How to create new System Verilog file on Questasim.....?
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Guru59



Joined: 10 Jul 2006
Posts: 235
Helped: 4
Post15 Nov 2007 6:01   

How to create new System Verilog file on Questasim.....?
I would like to practice system verilog on Questasim(6.2a) but i could not find System verilog file creation on Questasim (6.2a)...

Anyone Help.....!
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walid farid



Joined: 08 Nov 2006
Posts: 43
Helped: 15
Post15 Nov 2007 8:41   

Re: How to create new System Verilog file on Questasim.....?
ok,
I want to ask you to check the technotes
goto MainMenu >> Help > Technotes > sysvlog just to make sure that it supports
SystemVerilog because i don't know about old versions of QuestaSim.

If it supports SystemVerilog but there isn't SystemVerilog file creation, then its a bug so just open any source and save as .sv and it should work.

Regards
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mssajwan



Joined: 19 May 2006
Posts: 103
Helped: 10
Location: Banaglore
Post19 Nov 2007 9:22   

How to create new System Verilog file on Questasim.....?
Hi,
make a file & save it using .sv........then compile it using command:
qverilog -sv filename.sv

-Manmohan
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