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Doubt in system verilog
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deepu_s_s



Joined: 24 Mar 2007
Posts: 329
Helped: 13
Post14 Nov 2007 13:33   

Doubt in system verilog
Hi friends,

I didnt understand the concept of Unions in SV. Pls tell me any1 how unions are useful in system verilog. what are the difference between unions and structures? what are tagged unions.

and also what is the difference between packed structures and unpacked structures.


Thanks and regards
Deepak
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nan_ishan



Joined: 29 Oct 2007
Posts: 99
Helped: 10
Location: Nasik-India-Asia
Post14 Nov 2007 13:46   

Re: Doubt in system verilog
i CAN HELP U WITH DIFFERENCE OF UNION AND STRUCTURE:




wHEN U DECLARE VARIABLES IN A UNION ,THE MEMORY ALLOCATED TO A UNION IS OF THE SIZE OF MAXIMUM SIZE OF THE VARIABLE IN THE UNION AND NOT THE SUM OF THE SIZES OF VARIABLES....

Wheras in structure,the total memory allocated is the sum of the sizes of the variables....

Suppose u declare three variables of 2byte, 4byte ,and 8byte in union the memory allocated to union is of 8byte


u declare three variables of 2byte, 4byte ,and 8byte in Structure the memory allocated to structure is of 14byte.....
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deepu_s_s



Joined: 24 Mar 2007
Posts: 329
Helped: 13
Post14 Nov 2007 13:52   

Doubt in system verilog
hi nan,
suppose i declared 3 variables of different sizes..
var1 or 2 bytes
var2 of 4 bytes
var3 of 8 bytes.
According to above answer, are values of var1 and var2 are lost ?
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walid farid



Joined: 08 Nov 2006
Posts: 43
Helped: 15
Post15 Nov 2007 8:57   

Re: Doubt in system verilog
Hi,
1st about unions.....

suppose

a. Unpacked Union --->

module top();
typedef union {int a; bit b;} union1;
union1 a;

initial
begin
a.x = 1; // at time=0 x=1 and b=1
#2 a.x = 2; // at time=2 x=2 and b=0 because b points at x[0]
end

b. Packed Union --->
all the elements have to be of the same width or you will get an error :
#Packed union fields must all be the same width
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rakesh448



Joined: 14 Aug 2006
Posts: 9
Post30 Oct 2008 5:53   

Re: Doubt in system verilog
1.Unions when declared as packed are synthesizable and unpacked are not
synthesizble.

2. Packed Unions memory allocation is contiguous bits where as unpacked does
not have any order of memory allocation of there variables
3. Packed Unions allows part select and bit select where as unpacked doesn't
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ljxpjpjljx



Joined: 05 May 2008
Posts: 533
Helped: 12
Location: Shang Hai
Post31 Oct 2008 2:58   

Re: Doubt in system verilog
union share the memory space while the struct has independant memory!
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satishkumar



Joined: 02 Apr 2006
Posts: 73
Helped: 2
Location: bangalore
Post03 Nov 2008 12:04   

Doubt in system verilog
visit www.testbench.in
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