CPU @ RTL Design - Verilog (with complete documentation)

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yahootew3000

Joined: 20 Aug 2007
Posts: 26

14 Nov 2007 3:50 cpu design verilog

Introduction To The Design of CPU using RTL Approach.
This CPU is a simple 8-bit processor with 8-bit address bus. The architecture is based on accumulator-based design. The instruction set is grouped into few categories which is shown as below:

1. Data manipulation
a. ADD X Add the value in memory to the accumulator.
b. SUB X Subtract the value in memory to the accumulator.
c. XOR X Exclusive-OR logic operation value in memory to the accumulator.
d. AND X Perform AND logic operation value in memory to the accumulator.
e. ADR Add between registers.

2. Data transfer
a. MVI Move the immediate data to the specified register.
b. MVD Move the specified memory data to the specified register.
c. MOV Move data between registers.
d. LDA X Load the memory data to the accumulator.
e. STA X Load the accumulator to the memory data.

3. Program control
a. BRN X Branch if the value in the accumulator is negative.
b. JMP X Jump to a specified address.

6. Shifting
a. SHR Shift one bit of the register to the right.
b. SHL Shift one bit of the register to the left.

5. Miscellaneous
a. HALT Stay no operation.
b. NOP No operation until next instruction.

The design is using the Λltera Quαrtus II 7.2

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Last edited by yahootew3000 on 16 Dec 2007 11:44; edited 1 time in total

yahootew3000

Joined: 20 Aug 2007
Posts: 26

16 Dec 2007 11:23 open core for picoblaze

Eiffel.Z

Joined: 07 Dec 2007
Posts: 14
Location: China

17 Dec 2007 10:32 simple cpu verilog

yahootew3000
excuse me, I have no enough point to download the files. so can you mail these files to me? Thank you very much!
E-mail: yikoulian2001(at)126.com

best regards
Eiffel

master_picengineer

Joined: 03 Sep 2007
Posts: 1050
Helped: 62

18 Dec 2007 10:01 rapidshare verilog risc

Yes, this is too expensive. Please share it with Rapid share.
Thanks.

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

18 Dec 2007 10:14 kcpsm3.zip

All attached files are copied to the free mirror server about once per month, so it should happen soon.
Then you can download from the free mirror without using any points.

yahootew3000

Joined: 20 Aug 2007
Posts: 26

18 Dec 2007 16:47 design simple cpu using verilog

master_picengineer wrote:

Yes, this is too expensive. Please share it with Rapid share.
Thanks.

You can choose to download the documentation instead. The codes are included as well. The Verilog files are for your convenience

Added after 3 minutes:

I have included the winrar format, it is less in size compared to the winzip format. Both are the same.

RegUser_2

Joined: 24 Dec 2001
Posts: 235
Helped: 2

24 Dec 2007 20:19 simple cpu in verilog

For extra examples of CPU designs for FPGA, some can take a look at opencores.org (various RISC designs and popular PIC and AVR CPU cores what makes them very attractive because the software developments suites already exists).

Then some can also take look on the CIRCUIT CELLAR articles (ie issue 116 March 2000 Building a RISC System in an FPGA where all the gory story of developing both a 16-bit RISC and adapting retrgetable LCC compiler are described and source code is given).

Both Xilinx and LATTICE provide free optimized 8-bit CPU cores sources (PICOBLAZE and MACO8). PICOBLAZE description are all over the net and there is ongoing PACOBLAZE project which adds various perifery to the core and makes it less vendor dependent.

Eiffel.Z

Joined: 07 Dec 2007
Posts: 14
Location: China

28 Dec 2007 7:03 verilog documentation and2

yahootew3000
Hi, brother. I have a question when I simulate your code given to me. My tools is QII 5.0, and the RAM ipcore transfer result is not the same as your document mentioned. When read RAM, the Data of RAM may be appear at the next edge of the clock, there are some problem.
and I refer to the RAM Megafunction User Guide from Altera Website. The actual working operation is as my simulate status, so how you get the document result?

Johnson

Joined: 04 Oct 2004
Posts: 730
Helped: 22

28 Dec 2007 16:27 16-bit picoblaze

"Both Xilinx and LATTICE provide free optimized 8-bit CPU cores sources (PICOBLAZE and MACO8). PICOBLAZE description are all over the net and there is ongoing PACOBLAZE project which adds various perifery to the core and makes it less vendor "

They do not give you the main source code, so you can not do change on them.

8-bit address is very short address space, can you change it to 16-bit?

Based on what processor this one is designed? Also is it a RISC one?

RegUser_2

Joined: 24 Dec 2001
Posts: 235
Helped: 2

29 Dec 2007 0:59 how to design a simple processor in verilog

Johnson wrote:

ALL of them are RISC, ALL of them contain source code (optimized for FPGA families)

PACOBLAZE is less optimized but more universal

http://bleyer.org/pacoblaze/

Johnson

Joined: 04 Oct 2004
Posts: 730
Helped: 22

29 Dec 2007 8:23 cpu design with verilog

What about IDE and compiler suuport? Is assembler included?

salma ali bakr

Joined: 27 Jan 2006
Posts: 973
Helped: 80

29 Dec 2007 9:35 nnarm assembler

RegUser_2 wrote:

Johnson wrote:

ALL of them are RISC, ALL of them contain source code (optimized for FPGA families)

PACOBLAZE is less optimized but more universal

http://bleyer.org/pacoblaze/

so can i find easily the verilog source code of picoblaze on the net...?
not just diagrams..!!
do you have any sites that you use already for this...
thank youuuuuu Very Happy

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

29 Dec 2007 10:37 kcpsm3.v

Verilog and VHDL source code for PicoBlaze is downloadable from the Xilinx PicoBlaze lounge. You may need to register and login, but it's free. Look for files kcpsm3.v or kcpsm3.vhd in the ZIP archive.
http://www.xilinx.com/ipcenter/processor_central/picoblaze/member/
http://www.xilinx.com/ipcenter/processor_central/picoblaze/member/KCPSM3.zip

However, the source code contains many instantiated Xilinx flop and LUT primitives, so don't expect it to be easy to understand or easy to use with a non-Xilinx FPGA. It may have been hand-coded or translated from some other language.

Johnson

Joined: 04 Oct 2004
Posts: 730
Helped: 22

29 Dec 2007 14:01 design simple processor+verilog+fpga

echo47 wrote:

The xilinx wesite do not give you the source file! What you can get is just synthesized netlist and you can not modify or customize it!

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

29 Dec 2007 14:45 a simple processor design in verilog

Did you try downloading the file and looking inside? One Xilinx web page even says, "PicoBlaze for Spartan-3 design files now includes source Verilog and VHDL."

The code is at LUT/flop level, so it's difficult to understand, but the the author's comments say he did it that way on purpose.

Johnson

Joined: 04 Oct 2004
Posts: 730
Helped: 22

29 Dec 2007 16:57 processor verilog rtl code

We use "source code" for codes at high level and before synthesis, not "The code is at LUT/flop level", YOU CAN NOT EDIT IT!

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

30 Dec 2007 15:11 rtl design with d register

People sometimes write original code at the LUT/flop level, even though it's tedious work. In this message, the PicoBlaze author explains a little why he did it that way:
http://forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&message.id=68&query.id=2313#M68

The PicoBlaze code is editable, but it wouldn't be any fun. In this message, the author suggests editing the code to add a feature, but advises that it won't be easy:
http://forums.xilinx.com/xlnx/board/message?board.id=PicoBlaze&message.id=23&query.id=2289#M23

RegUser_2

Joined: 24 Dec 2001
Posts: 235
Helped: 2

31 Dec 2007 10:11 mico32 instruction set assembly

Lattice distributes free MICO8 and MICO32 RISC cores with verilog sourve code. MICO32 is a high performance 32-bit RISC system which already got ported to other vendors FPGA's (Spartan 3). It's code is not specific to any FPGA vendor, except for the Lattice specific JTAG core. It implements wishbone internal bus what makes it easy to incorporate other open cores. MICO32 have GCC C compiler devised for it's software development

There are ARM clones (nnARM) and OpenRISC (OR1200) cores some can find on the web.

All this at the top of various cores of popular PIC and AVR 8-bit clones available on the opencores.org site.

Johnson

Joined: 04 Oct 2004
Posts: 730
Helped: 22

31 Dec 2007 15:31 rtl approach in verilog

Is there any unified software and hardware development environment for Lattice cpu core?

guoshaojun

Joined: 02 Jan 2008
Posts: 5

02 Jan 2008 13:32 verilog simple cpu

this is too expensive. Please share it with Rapid share.
Thanks.

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

02 Jan 2008 23:11 simple processor + verilog project

Hi guoshaojun, if you are referring to the RAR files in the first message, then you can click the "Free Mirror" links to download the files without using any points.

atena

Joined: 22 Feb 2007
Posts: 98
Helped: 5

03 Jan 2008 8:53 kcpsm3.v

yahootew3000 wrote:

Not exactly mistake but i think you have forgoten some important point. Allow me to fulfill your datasheet as much as i can plz, firstly we should also mention about the Interupt, for example with the simple processor like 85 we can have non-maskable interupt like TRAP ( we can define in VHDL as the infinite loop without EXIT instruction ) and obviously the maskable interupt infinite loop with conditional exit instruction, the interupt priority also should be considered.
Secondly you havent mentioned about the flag register, so that we can have the conditional jump instruction. With flag register will be tie with Acc... etc..
The concept of making a CPU or MPU is simply the concept of user defined data types, with each every instruction we enter ( can be done by define : type instruction is ) it will automatically do one or a group of predefine procedures.
But anyway, your concept is correct and from it we can make a simple CPU.

However, i have a question that i havent satisfied with my own answer till now. We know that with a MPU ( micro processor ) we consider 2 types of instruction : 1st 1 byte instruction such like in 8085 we have MOV A,B and the schedule clock cycle for it is 4. And 2 Byte instruction like MVI A,#data with 7 clock cycle. My question is : Why with the ins MVI A,#data the scheduled clk cycle is not 8 as the multiple of 4 ? Because the required opcode for MVI and MOV are both 1 byte, as the ip data.
Can any SYNOPSYS Tools like Design Compiler or Prime Time solve this problem ? If yes somebody plz explain me in detail ? Thanks in advance.

yahootew3000

Joined: 20 Aug 2007
Posts: 26

27 Jan 2008 7:16 1 byte shift register verilog

Eiffel.Z wrote:

yahootew3000
Hi, brother. I have a question when I simulate your code given to me. My tools is QII 5.0, and the RAM ipcore transfer result is not the same as your document mentioned. When read RAM, the Data of RAM may be appear at the next edge of the clock, there are some problem.
and I refer to the RAM Megafunction User Guide from @ltera Website. The actual working operation is as my simulate status, so how you get the document result?

Hi, i simulated the codes using QII 7.1. It doesn't cause any problem to me. The documentation included the codes for each module. I design the simple CPU through hierarchical technique. Maybe you can try to pick some modules and give a test, chek whether it is same like mine.

Added after 3 minutes:

atena wrote:

yahootew3000 wrote:

Hi,
I guess my design is just an introduciton to CPU design, speficically for beginner. Not as complex as the 85. SO, it only have the most fundamental operation only. I can say that it has the simply ISA (Instruction Set Architechture). Anywhere, thank for your comment.