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bala9383
Joined: 01 Jun 2007
Posts: 30
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 02 Nov 2007 7:51 Latch and Flip-Flop |
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1. 1. Is Latch is a sequential ckt.???
If so, explain?
2. As Latch doesnt have a clock signal, how it can be called as a sequential circuit??
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onlymusic16
Joined: 19 Sep 2007
Posts: 133
Helped: 3
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| 02 Nov 2007 8:09 Re: Latch and Flip-Flop |
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Any circuit that can hold data is a sequential circuit, thats the main difference between a combo logic and sequential logic.
Hope that helps.
Added after 50 seconds:
hold data (store data), should not be confused with hold time:D
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rameshchand
Joined: 11 Sep 2007
Posts: 115
Helped: 30
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| 02 Nov 2007 10:15 Re: Latch and Flip-Flop |
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| latch is a sequential circuit only difference between latch & flipflop is latch is a level triggering device flipflop is a edge triggering device.
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sekapr
Joined: 27 Jul 2006
Posts: 100
Helped: 5
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| 07 Nov 2007 4:21 Re: Latch and Flip-Flop |
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| latch is a sequential circuit
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quan228228
Joined: 23 Mar 2006
Posts: 212
Helped: 12
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| 07 Nov 2007 5:06 Re: Latch and Flip-Flop |
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Latch has clock input.
And Flip-flop is composed of two latches.
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salma ali bakr
Joined: 27 Jan 2006
Posts: 918
Helped: 74
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| 07 Nov 2007 10:40 Re: Latch and Flip-Flop |
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when a circuit has a state (its output depends not only on the current input, but also on the previous inputs) then it's considered a sequential circuit or logic 
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vamsi_addagada
Joined: 05 Jul 2007
Posts: 86
Helped: 3
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| 07 Nov 2007 21:39 Latch and Flip-Flop |
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hi
latch is level triggerinng is the contain haveenable signal .FF are edge triggering .ff are made up with latch
vamsi krishna
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mohaddin
Joined: 24 Nov 2005
Posts: 15
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| 03 May 2008 17:29 Latch and Flip-Flop |
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Hi
Latch is a level sensitive, but FF is a edge triggered.
regards
Moha
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sykab
Joined: 26 Apr 2008
Posts: 36
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| 04 May 2008 0:55 Re: Latch and Flip-Flop |
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Latch is called a sequential circuit because it doesn't depend only on its actual inputs. It also depends on its previous state, this is, the previous output.
Look at this image
Good luck
Last edited by sykab on 06 May 2008 23:01; edited 1 time in total |
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badola
Joined: 04 Jan 2008
Posts: 86
Helped: 1
Location: bangalore
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| 05 May 2008 5:09 Re: Latch and Flip-Flop |
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Both latches and flip-flops are circuit elements whose output depends not only on the present inputs, but also on previous inputs and outputs.
They both are hence referred as "sequential" elements.
In electronics, a latch, is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby can store one bit of of information. Today the word is mainly used for simple transparent storage elements, while slightly more advanced non-transparent (or clocked) devices are described as flip-flops. Informally, as this distinction is quite new, the two words are sometimes used interchangeably. [wiki]
In digital circuits, a flip-flop is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory. Today, the term flip-flop has come to generally denote non-transparent (clocked or edge-triggered) devices, while the simpler transparent ones are often referred to as latches.[wiki]
A flip-flop is controlled by (usually) one or two control signals and/or a gate or clock signal.
Latches are level sensitive i.e. the output captures the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes.
Flip-Flops are edge sensitive i.e. flip flop will store the input only when there is a rising or falling edge of the clock.
A positive level latch is transparent to the positive level(enable), and it latches the final input before it is changing its level(i.e. before enable goes to '0' or before the clock goes to -ve level.)
A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for negative edge flop) only.
Latches are faster, flip flops are slower.
Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.
Latches take less gates (less power) to implement than flip-flops.
D-FF is built from two latches. They are in master slave configuration.
Latch may be clocked or clock less. But flip flop is always clocked.
For a transparent latch generally D to Q propagation delay is considered while for a flop clock to Q and setup and hold time are very important.
Synthesis perspective: Pros and Cons of Latches and Flip Flops
In synthesis of HDL codes inappropriate coding can infer latches instead of flip flops. Eg.:"if" and "case" statements. This should be avoided sa latches are more prone to glitches.
Latch takes less area, Flip-flop takes more area ( as flip flop is made up of latches) .
Latch facilitate time borrowing or cycle stealing whereas flip flops allow synchronous logic.
Latches are not friendly with DFT tools. Minimize inferring of latches if your design has to be made testable. Since enable signal to latch is not a regular clock that is fed to the rest of the logic. To ensure testability, you need to use OR gate using "enable" and "scan_enable" signals as input and feed the output to the enable port of the latch. [ref]
Most EDA software tools have difficulty with latches. Static timing analyzers typically make assumptions about latch transparency. If one assumes the latch is transparent (i.e.triggered by the active time of clock,not triggered by just clock edge), then the tool may find a false timing path through the input data pin. If one assumes the latch is not transparent, then the tool may miss a critical path.
If target technology supports a latch cell then race condition problems are minimized. If target technology does not support a latch then synthesis tool will infer it by basic gates which is prone to race condition. Then you need to add redundant logic to overcome this problem. But while optimization redundant logic can be removed by the synthesis tool ! This will create endless problems for the design team.
Due to the transparency issue, latches are difficult to test. For scan testing, they are often replaced by a latch-flip-flop compatible with the scan-test shift-register. Under these conditions, a flip-flop would actually be less expensive than a latch. Read a good article on problems of latch published in eetimes long back !!
Flip flops are friendly with DFT tools. Scan insertion for synchronous logic is hassle free.
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kumar_eee
Joined: 22 Sep 2004
Posts: 349
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| 06 May 2008 20:37 Re: Latch and Flip-Flop |
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| Do you need more than these info?.
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anishjp
Joined: 04 Jan 2008
Posts: 49
Location: "Gods own country".. Kerala
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| 09 May 2008 10:51 Latch and Flip-Flop |
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| Badola, that was a great work.....Thanks
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asicganesh
Joined: 18 Oct 2007
Posts: 51
Helped: 1
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| 09 May 2008 11:42 Latch and Flip-Flop |
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| I think bala9383 got confused between synchronous circuit and sequential circuit..
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basha_vlsi
Joined: 19 Mar 2008
Posts: 23
Helped: 2
Location: Hyderabad, India
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| 10 May 2008 8:57 Re: Latch and Flip-Flop |
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As latch can hold (store) data it is a seq element
more over latch is level triggered and flop is edge triggered
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ljxpjpjljx
Joined: 05 May 2008
Posts: 83
Helped: 2
Location: Shang Hai
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| 12 May 2008 4:34 Re: Latch and Flip-Flop |
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| latch is level sensitive, register is edge sensitive!
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