About the logic level change in DDR SDRAM

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EDA_hg81

Joined: 25 Nov 2005
Posts: 395

31 Oct 2007 21:31 About the logic level change in DDR SDRAM

According to the DDR SDRAM datasheet from Micron, the logic level of CKE is going to be changed from LVCMOS low to SSTL 2 high during system initialization.

How I can do this in FPGA programming.

Thanks

Iouri

Joined: 17 Aug 2005
Posts: 687
Helped: 79

01 Nov 2007 17:44 About the logic level change in DDR SDRAM

you need to assign you IO standard in your USF file (I assume you are using Xilinx)

EDA_hg81

Joined: 25 Nov 2005
Posts: 395

01 Nov 2007 21:02 Re: About the logic level change in DDR SDRAM

I know I have too assign it in UCF file.

but How I can change the logic level during the operation from LVCOMS to SSTL_2?

Iouri

Joined: 17 Aug 2005
Posts: 687
Helped: 79

01 Nov 2007 22:47 About the logic level change in DDR SDRAM

there are only two logic levels high and low, all you need to do it just switch from low to high, because you are doing this during init stage it doesn't really matter which standard is that, as far as you within limits of 2.5V being logical high