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The size of pmos pass transistor in LDO regulator


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rogerqin



Joined: 12 May 2006
Posts: 16


Post30 Oct 2007 8:18   

pmos pass transistor


Hi, all
I am designing a LDO regulator, the minimal power supply voltage is 4.75V, and the output voltage is 4.5V, the maximum output current is 20mA. In order to assure the pmos pass transistor operating in saturation, I have to set a large W/L, but i can not provide this area.
My question is that if I choose a smaller size, then the transistor of pmos pass transistor may operate in triode region. What performance of regulator will degrade?
When I simulate, I found that only the psr performance degrades.
Is there anyone have the experience about this problem? Thanks for your help.
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rameshchand



Joined: 11 Sep 2007
Posts: 118
Helped: 31


Post30 Oct 2007 8:25   

ldo triode


hi


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hung_wai_ming@hotmail.com



Joined: 05 Jan 2004
Posts: 376
Helped: 39


Post31 Oct 2007 5:01   

transistor sizes as of 2007


Did u simulate output noise and transient loading output variation? I think both of them should be degraded as well.

If all three performances are not of your concern, you can go ahead to use it in triode region.
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rogerqin



Joined: 12 May 2006
Posts: 16


Post31 Oct 2007 5:15   

ldo with pmos pass gate


I have simulate the transient loading variation, it seems no problem. I have not simulate the output noise, but only power supply rejection, which is decreased about 10dB than the condition that the pmos pass transistor operating in saturation region.
If I can accept the decrease of psr, I am not sure whether there is other problems.
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hung_wai_ming@hotmail.com



Joined: 05 Jan 2004
Posts: 376
Helped: 39


Post31 Oct 2007 5:28   

calculating transistor size for ldo


You may try simulate large loading current variation and your PMOS will go even deeper in triode region. Actually, what u need to consider is in real system, the transient loading can be larger than your expectation, not necessarily in your 20mA as 20mA is JUST a DC value, not peak-to-peak value. Your PSRR may create problems if your LDO used in RF system.
As your PMOS is in triode region, your output impedance can get smaller and so it would affect your PM, which can be worse
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Post31 Oct 2007 5:28   

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niezimei



Joined: 01 Dec 2006
Posts: 28
Helped: 2


Post01 Nov 2007 7:04   

pmos pass transistor saturation ldo


when pass transistor operates in triode region the loop gain will decrease drasticly.In order to get a reasonable gain error, make sure the loop gain is larger than 60db even at worse case.
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stoned



Joined: 23 Feb 2006
Posts: 56
Helped: 5


Post01 Nov 2007 10:14   

pass transistor pmos


But PSRR is the Key performance for the most application of LDO
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iamxo



Joined: 22 Mar 2006
Posts: 1031
Helped: 564
Location: Southeast Asia


Post02 Nov 2007 3:31   

ldo region


the pass device size is only decided by the maximum output current.

and in light load, ofcourse the pass device will be in triode. so you should keep loop gain large enough at all loads.
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quanble



Joined: 07 Jul 2006
Posts: 8


Post07 Nov 2007 8:27   

pmos vs nmos ldo pass transistor


PMOS size is decided by max output current .You must make the pass MOS gate voltage still keep the input diff pair and pass MOS in saturation region .
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krishnareddy



Joined: 26 Nov 2007
Posts: 16


Post18 Dec 2007 17:36   

pass transistor in ldo


pmos transistor size depends on maximum load current,available vgs for the pass transistor and drop out voltage.
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arghpok



Joined: 13 Feb 2007
Posts: 38
Helped: 1


Post27 Dec 2007 17:42   

simulate the output impedance of ldo regulator


Is your pass transistor working all the time in triode region ? It would be a big trouble if you have it working at triode and saturation as well. As you know, the expression for the current change from square behavior to logarithmic, this might lead you to undesirable effects such as lower ripple rejection, transient response and furthermore, stability issues due to the "slewing" (not the electrical concept) you introduce when working at triode region.
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