OOPS in System Verilog

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vjm16

Joined: 19 Sep 2007
Posts: 21
Helped: 5

04 Oct 2007 13:17 systemverilog oop

Hi all,

Is it necessary to have deep understanding of oops in order to learn system verilog? (Don't mind, as Iam new to system verilog)

Thanks in advance,
vjm

mssajwan

Joined: 19 May 2006
Posts: 103
Helped: 10
Location: Banaglore

04 Oct 2007 14:06 system verilog oops concept

Nop....good if u know verilog......as u will start u will get to know.

-Manmohan

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vizpal

Joined: 26 Apr 2007
Posts: 43

05 Oct 2007 7:49 oops concepts in system verilog

Just have some basic understanding in OOP and C++...
You can start reading the SV lrm and u will understand these concepts.... No need to get worried abt OOP and C++ !!!!

anant

Joined: 20 Sep 2004
Posts: 49
Helped: 3

08 Oct 2007 6:12 learn system verilog

if you have used vera / e don't , concepts are the same.
no need to learn c++.

foster_cn

Joined: 14 Jan 2003
Posts: 74
Helped: 2

15 Oct 2007 7:56 systemverilog oops concepts

definitely, oop concept is helpful to pick up. pls see this thread also:
http://www.edaboard.com/ftopic275946.html

ahliang

Joined: 25 Jun 2006
Posts: 13

15 Oct 2007 13:05 oops in systemverilog

just to start ,no nend to study opp language

sanjay11

Joined: 07 Dec 2006
Posts: 32

16 Oct 2007 9:05 oops in system vrilog

no neccesary to know oop completely but basic understaning is essential.
Refer to Chris Spear's System Verilog book.

Regards,
Sanjay

donald007

Joined: 28 Aug 2007
Posts: 11
Helped: 1
Location: TAIWAN

17 Oct 2007 0:58 systemverilog profile

You can learn basic concept of OOP, then you can start to use SystemVerilog. Try example code is helpful.

www.testbench.in

Joined: 04 Jun 2008
Posts: 46
Helped: 2

18 Jun 2008 3:42 systemverilog oop basics

Just start learning SV,

U can learn OOPs using SV. No need to have prior knowledge of oops to start SV.

Gopi
www.testbench.in

boardlanguage

Joined: 06 Apr 2007
Posts: 96
Helped: 4

18 Jun 2008 16:28 spear verilog

As the other people have said, a background in OOP is helpful, but not absolutely necessary to start Systemverilog.

Systemverilog has several different areas of focus: design & modeling (RTL), verification (TB), assertions & coverage.

The verification(TB) aspect is definitely the most challenging. And here's where a background in OOP, or another HVL (like e or VERA) really helps.

I would focus on learning the RTL constructs first, practice them a little bit, then tackle the TB constructs next.

bywater

Joined: 17 Dec 2005
Posts: 11
Helped: 1

06 Sep 2008 8:30 how oops can be implemented in system verilog

vjm16 wrote:

Hi all,

Is it necessary to have deep understanding of oops in order to learn system verilog? (Don't mind, as Iam new to system verilog)

Thanks in advance,
vjm

That will be helpful if you get a basic acknowledge of OOP.