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saad
Joined: 08 Jun 2005
Posts: 63
Helped: 2
Location: Southampton, United Kingdom
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 12 Sep 2007 0:49 Differential Pair Transconductance!!! |
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Hi Everyone!!!
I am using pMOS input differential pair in a single stage opamp. I want to increase the transconductance (gm) of the input pair. I increase aspect ratio (W/L) to decrease Vdsat; hence expecting gm to increase.
On the other hand; Vds drop is decreased whereas Vdsat and gm remain almost unaffected (simulation results are given below). How can I keep Vds constant or increase gm instead? Can anyone help?
W/L = 60
Name: m1
Model: cmosp
Id: -9.90e-05
Vgs: -9.39e-01
Vds: -5.28e-02
Vbs: 0.00e+00
Vth: -5.07e-01
Vdsat: -3.59e-01
Gm: 2.15e-04
Gds: 1.73e-03
Gmb 8.41e-05
W/L=120
Name: m1
Model: cmosp
Id: -9.95e-05
Vgs: -9.14e-01
Vds: -2.70e-02
Vbs: 0.00e+00
Vth: -5.08e-01
Vdsat: -3.44e-01
Gm: 2.25e-04
Gds: 3.54e-03
Regards,
Saad
Last edited by saad on 12 Sep 2007 15:47; edited 1 time in total |
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DenisMark
Joined: 16 Sep 2005
Posts: 307
Helped: 61
Location: Russia
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| 12 Sep 2007 8:16 Re: Differential Pair Transconductance!!! |
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How I can see ur pmos input transistors work in triode regione (Vds too low). It seems something is wrong in ur circuit or in testbenches.
U should to bias input pair in saturation region, ever they need to work in weak inversion (sub-threshold, |Vgs-Vth|<=-50mV). In weak inversion Gm=Id/(n*Vt), n=1.3..1.5, Vt=kT/q. So futher increase of Gm is only achivable with Id increasing.
I give u usefull reference, i think they will be usefull to u.
http://www.edaboard.com/viewtopic.php?p=762910#762910
http://www.edaboard.com/viewtopic.php?p=621110#621110
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saad
Joined: 08 Jun 2005
Posts: 63
Helped: 2
Location: Southampton, United Kingdom
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| 12 Sep 2007 13:06 Re: Differential Pair Transconductance!!! |
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| DenisMark wrote: |
How I can see ur pmos input transistors work in triode regione (Vds too low). It seems something is wrong in ur circuit or in testbenches.
U should to bias input pair in saturation region, ever they need to work in weak inversion (sub-threshold, |Vgs-Vth|<=-50mV). In weak inversion Gm=Id/(n*Vt), n=1.3..1.5, Vt=kT/q. So futher increase of Gm is only achivable with Id increasing.
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I am biasing differential pair with constant current source (100uA) and you can see the operating current is 99uA (and it seems to me that device is operating in saturation).
What do u think?
I have attached the opamp schematic too. I am getting extremely poor gain (dont know whats wrong  ) Please check if cascodes in the gain stage are biased correctly or not?
Regards,
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DenisMark
Joined: 16 Sep 2005
Posts: 307
Helped: 61
Location: Russia
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| 12 Sep 2007 14:10 Differential Pair Transconductance!!! |
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It isn't clear. What voltage values at gate, source, drain nodes?
May be common mode voltage at inputs of opamp is too low. For ur circuit the bottom ICMR is VgsN(M3,M4)-VthP(M1,M2). I can suggest that u set input to ground potential (but ur circuit don't allow this) or overdrive voltage of NMOS is too high(increase W/L ratio of NMOS).
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saad
Joined: 08 Jun 2005
Posts: 63
Helped: 2
Location: Southampton, United Kingdom
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| 12 Sep 2007 14:55 Re: Differential Pair Transconductance!!! |
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I have set W/L of M3,4 to be same as W/L for M10 (for proper mirroring) to be 5.
How would W/L of M10 affect the output resistance and hence gain of the amplifier??? Gain is really poor (Av=10)
Please see if i m biasing cascodes right or not??
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DenisMark
Joined: 16 Sep 2005
Posts: 307
Helped: 61
Location: Russia
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| 12 Sep 2007 15:06 Differential Pair Transconductance!!! |
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Biasing of cascode don't have influence of PMOS pair operation point. At the picture all looks ok. M14 and M18 must have lager W/L ratio than M9,M10 and M7,M8 so that devices operates in saturation ever in worst case (max current, max temperature).
U must provide me operation point information regarding M1,M3 and voltages at their terminals to resolve ur primary problem.
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tirnanog
Joined: 10 Sep 2007
Posts: 3
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| 12 Sep 2007 15:09 Differential Pair Transconductance!!! |
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As DenisMark has already asked: What is your common mode input voltage?
If this is too low then devices M1 & M2 would be out of saturated region and acting just as switches with low output impedance giving you low gain.
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saad
Joined: 08 Jun 2005
Posts: 63
Helped: 2
Location: Southampton, United Kingdom
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| 12 Sep 2007 15:19 Re: Differential Pair Transconductance!!! |
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In order to keep M9 in saturation its gate voltage must be Vt+Vdsat above its source voltage (i.e. Vdsat10). (W/L) of M14 is (1/5)(W/L)of M9 forcing Vg14 to be above Vt+2Vdsat hence keeping M9 to be in saturation.
Please correct me if i am doing it wrong!!
i can post node voltages of most of the transistors in the amplifier in some time. till then please check if i m correctly considering biasing??
Thanks
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DenisMark
Joined: 16 Sep 2005
Posts: 307
Helped: 61
Location: Russia
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| 12 Sep 2007 15:28 Differential Pair Transconductance!!! |
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It's correct, but u should check this condition over PVT and in worst case.
Give me operation point information regarding M1,M3 and voltages at their terminals to resolve ur primary problem.
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saad
Joined: 08 Jun 2005
Posts: 63
Helped: 2
Location: Southampton, United Kingdom
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| 12 Sep 2007 15:29 Re: Differential Pair Transconductance!!! |
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| tirnanog wrote: |
As DenisMark has already asked: What is your common mode input voltage?
If this is too low then devices M1 & M2 would be out of saturated region and acting just as switches with low output impedance giving you low gain. |
For AC analysis, I am using 1V AC signal.
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tirnanog
Joined: 10 Sep 2007
Posts: 3
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| 12 Sep 2007 15:41 Differential Pair Transconductance!!! |
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| What is the dc voltage that is being applied at the gate of M1 and M2?
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saad
Joined: 08 Jun 2005
Posts: 63
Helped: 2
Location: Southampton, United Kingdom
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| 12 Sep 2007 15:45 Re: Differential Pair Transconductance!!! |
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| DenisMark wrote: |
U must provide me operation point information regarding M1,M3 and voltages at their terminals to resolve ur primary problem. |
Here are the node voltages (attachment). I m using 1V AC signal for AC analysis.
Please check if something is wrong.
W/L of all the transistors are as follows
M1,M2 = Kc
M3,M4,M6,M9,M10 = Kb
M14,M16,M19 = Kb/5 (for proper biasing)
M17 = Ka/5 (for proper biasing)
M5,M7,M8 = Ka
M11,M12,M13,M18 = 2*Ka
where Ka=15, Kb=5, Kc=60
See if anything is problematic!!
Thanks
Last edited by saad on 12 Sep 2007 15:49; edited 1 time in total |
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saad
Joined: 08 Jun 2005
Posts: 63
Helped: 2
Location: Southampton, United Kingdom
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| 12 Sep 2007 15:46 Re: Differential Pair Transconductance!!! |
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| tirnanog wrote: |
| What is the dc voltage that is being applied at the gate of M1 and M2? |
It will be short circuited for AC analysis anyways.. does applying DC voltage matter?? atleast i dont think so
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tirnanog
Joined: 10 Sep 2007
Posts: 3
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| 12 Sep 2007 15:51 Differential Pair Transconductance!!! |
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Yes.
From looking at the operating point information that you provided it looks like you have a dc voltage of 0V at the gate of M1 and M2 and I think that is your problem. This voltage needs to be higher. How do you setup the input stimulus?
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DenisMark
Joined: 16 Sep 2005
Posts: 307
Helped: 61
Location: Russia
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| 13 Sep 2007 5:46 Differential Pair Transconductance!!! |
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Ok, VgsM3=0.996V and VthM1=0.508 so minumum of ICMR is VgsM3-VthM1=0.488V. So if dc voltages on the gates of M1 & M2 low than 0.488 their will enter in triode region.
It looks like u don't build testbench correctly. Yes, the inputs must be tied to AC ground and AC source must present in series with one of them, but it doesn't mean that the inputs must be connected to DC ground.
Apply DC source to positive input (more than VgsM3-VthM1 and low than Vdd-VgsM1-VdsatM11), short output and negative input through inductance 1H (short during DC analisys, open circuit during AC), short negative input to ground through capacitance 1F also (open - DC, short - AC). So ur input common mode voltage will be determinated by DC source. Place AC source. It doesn't matter in series to positive or negative input, it affect on initial phase shift only. Amplitude of AC source also doesn't matter, it only affect on output voltage amplitude, not the gain or phase, it can be 1V, 1kV, 1pV, etc.
After all do DC operation point and AC simulation. Difference between positive and negative inputs will be offset voltage.
If u want to decrease lowest boundary of ICMR u can tie bulk contacts of M1&M2 to supply rail. So u increase VthM1 due to body effect. If body effect is strong u can obtain ICMR begining from 0V.
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srik10
Joined: 26 Sep 2007
Posts: 2
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| 08 Oct 2007 2:23 Differential Pair Transconductance!!! |
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Just curious,
Whats op-amp topology is this? looks like a diff pair followed by a Cascode + Folded cascode. Is that right ?
What is the advantage of using this over a folded cascode amp ??
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rajanarender_suram
Joined: 20 Jan 2006
Posts: 174
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| 10 Oct 2007 8:42 Differential Pair Transconductance!!! |
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from your node voltages for M1 nad M2 vds<vdsat that means these transistors are in linear region.
Thats is you main problem
Added after 4 minutes:
what about the node volt of m11
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tarun_taurus
Joined: 15 Feb 2005
Posts: 28
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| 10 Oct 2007 11:39 Re: Differential Pair Transconductance!!! |
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Ur transistors are in Triode region and you need to define DC for your gate. before starting AC analysis DC operating pt. is established.
as someone rightly suggested, you need to increase Gate voltage of PMOS to reduce VDSAT and Increase Vds.
u get poor gain because the transistors are running in triode region.
Do .OP analysis before doing any other analysis & ensure transistors are in saturation.
--
Mt
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ftxhh
Joined: 27 Oct 2007
Posts: 2
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| 29 Oct 2007 18:42 Differential Pair Transconductance!!! |
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Hi saad,
As suggested, the input pmos pairs are in triode region, cause vdsat=0.34v and vds=0.0203v,which is lower than vdsat. I think you can increase the input pmos's bias voltage.
Best regards!
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rania_hassan
Joined: 29 Apr 2005
Posts: 107
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Location: Egypt
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| 31 Oct 2007 17:52 Re: Differential Pair Transconductance!!! |
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I don't prefer the usage of PMOS as input diff pair as it needs larger W/L to get the same gm that can be achieved by smaller NMOS
so it really limits your max operating frequency
best regards,
Rania
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ftxhh
Joined: 27 Oct 2007
Posts: 2
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| 01 Nov 2007 18:48 Re: Differential Pair Transconductance!!! |
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Re:
I don't prefer the usage of PMOS as input diff pair as it needs larger W/L to get the same gm that can be achieved by smaller NMOS
so it really limits your max operating frequency
best regards,
Rania
Hi Rania,
PMOS's 1/f noise performance is better than NMOS, and PMOS can be sited in NWEL, so PMOS as input diff pair input is more popular. However, as you say, PMOS has smaller gm for the same size. We can improve its bandwidth by increasing the current.
mouse
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layes2
Joined: 03 Dec 2004
Posts: 334
Helped: 5
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| 20 Nov 2007 14:07 Re: Differential Pair Transconductance!!! |
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| should be the same as one mos
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zxj_abc
Joined: 20 Nov 2007
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| 27 Nov 2007 14:35 Re: Differential Pair Transconductance!!! |
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| The input bias voltage is too low to make the input different pair working in saturating zone.
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phosphor_zhu
Joined: 29 Oct 2007
Posts: 19
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| 02 Dec 2007 12:58 Re: Differential Pair Transconductance!!! |
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i think you must make sure the pmos works on the edge of saturation.
and then, make the bias current bigger.
besides you may check out all ur pmos and nmos to see their op region
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haff99
Joined: 10 Mar 2007
Posts: 31
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| 02 Dec 2007 18:06 Re: Differential Pair Transconductance!!! |
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As already has been stated the diff pair is in triode. You have several options to fix this.
1. Tie the bodies of the diff pair off to the supply instead of to the source. The body effect increases the threshold value and your VDS will increase. This may not solve the issue though.
2. Add a PMOS level shifter to the diff pair.
3. Increase the bias current.
If you want to increase the gain you can also scale up the mirror devices of the diff pair from m=1 to m=?? whatever you want.
Also when you look at the gain it is easiest to close the loop like you are testing a op amp. Since you are cascoding the ouput, you don't have true rail to rail swing on your output. you can not put he comparator into unity game at some very low or very high voltage, like 100mV or something close to your rail. Your output can not pull down that low or pull that high. That is going to give you a very low db reading if you try to test the gain that way.
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gpwu
Joined: 08 Dec 2007
Posts: 48
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| 08 Dec 2007 2:48 Re: Differential Pair Transconductance!!! |
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Looks like M9 is in triode region, need to adjust bias point.
Increase bias I can increase gm.
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lijianheng
Joined: 29 Sep 2006
Posts: 133
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| 15 Dec 2007 5:58 Re: Differential Pair Transconductance!!! |
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| Maybe Vdas is too low, and the mosfet isn't work in the saturation region.
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gaom9
Joined: 08 Oct 2007
Posts: 123
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| 22 Dec 2007 4:22 Re: Differential Pair Transconductance!!! |
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Hi,
I am a newer of analog circuit design. I have a questions about this circuit.
How does the bia part which consist of m14 m18 m17 m19 m13 m16 and m12 of this circuit work? How can them provide a constant current to bia the diff pair.
Thank you!
Best regards!
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Tahar
Joined: 15 Feb 2005
Posts: 92
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| 26 Dec 2007 12:24 Re: Differential Pair Transconductance!!! |
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| rania_hassan wrote: |
I don't prefer the usage of PMOS as input diff pair as it needs larger W/L to get the same gm that can be achieved by smaller NMOS
so it really limits your max operating frequency
best regards,
Rania |
reduced flicker noise and Better matching is to trade for Bandwidth for choosing either PMOS or Nmos input pair.
For medium frequency range and a common voltage sustainable by both type, Pmos input pair is THE choice because the current that you save in case of Nmos shall not compensate for a better matching or a better working circuit.
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Canosa
Joined: 23 Mar 2007
Posts: 3
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| 06 Jan 2008 23:18 Re: Differential Pair Transconductance!!! |
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Some transistors are in triode, you have to put them in saturation before get gain make shura that DC operating point of all trasistors are stabilish in saturation.
The circuit that i use to bias the cascodes of the third stage of the amplifier are quiet different. I usually used two transistor with their gates connected and of then will be in triode and the other in saturation. The triode transistor had 3 times L than saturation trasistor to get the best headroom as possible to the output.
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