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pipeline in ASIC design

 
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siva_7517



Joined: 16 Jan 2006
Posts: 136


Post06 Sep 2007 12:35   pipeline in ASIC design

Hi,

I would like to know what is the benefit to have a long pipeline in the design.

as for my knowledge, the pipeline is used to increase the instruction throughput.
is there any suggestion?

thanks
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negreponte



Joined: 26 Sep 2004
Posts: 94


Post06 Sep 2007 13:21   Re: pipeline in ASIC design

Some benefits of pipeline design are:
increase of throughput (shorter critical path)
decrease of power (avoiding glitches and balancing the paths)
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2M



Joined: 31 Aug 2007
Posts: 11


Post06 Sep 2007 14:28   pipeline in ASIC design

hi

as long as the instructions are independent from each other :
deeper pipeline will have the better execution rate of instructions .
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dinaganesh



Joined: 17 Apr 2007
Posts: 15


Post06 Sep 2007 20:49   Re: pipeline in ASIC design

hi

actually basic concept behind pipelining is to reduce the execution speed of the processors.
normally execution of instruction takes place one after the other , but in pipeling concept, when the execution goes to the 2 nd cycle of first instruction ,at the same time the execution of the 1st cylce of the second instruction takes place.. so that the execution speed is almost reduced to half .
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Thinkie



Joined: 26 May 2005
Posts: 174
Helped: 14


Post06 Sep 2007 22:53   pipeline in ASIC design

Pipelining is good to increase the MHz speed of a design as the reg-to-reg paths are shorter.

However, the downside is that it takes more clocks to get the result (latency) and if it is a processor you take a bigger hit when you have to flush the pipeline (for example in a unpredicted branch).

So... it is not necessary a good thing... but in many cases it is...
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funzero



Joined: 19 Nov 2004
Posts: 203
Helped: 8


Post07 Sep 2007 14:38   Re: pipeline in ASIC design

Pipeline help to get more throughputs.But the data to process must not have releationship ,or the pipeline may not be able to execute.In cpu, not all instructions have same pipeline depth , it is difficult to relize the prediction circuit. In asic design , the approach is to gain process rate with area penalty .
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