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Read clk> wr_clk

 
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vlsi_freak



Joined: 03 Sep 2007
Posts: 84
Helped: 4
Post05 Sep 2007 13:03   Read clk> wr_clk
What will happen if FIFO read clock is very much greater than FIFO write clock.
How will i synchronize such a case when the read domain requires continous read operation

Thanks in advance
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rjainv



Joined: 18 Feb 2007
Posts: 147
Helped: 14
Location: Bangalore, India
Post05 Sep 2007 18:52   Re: Read clk> wr_clk
your width of write port should be greater than read port by atleast as much times as the ratio of rd_clk_frq/wr_clk_frq.
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