avimit
Joined: 16 Nov 2005
Posts: 415
Helped: 68
Location: Fleet, UK
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 05 Sep 2007 10:32 Re: Dynamic gates!! |
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Dynamic logic:
Consider a 4 input normal CMOS nand gate. There are 4 p trnasistors in series. P trans are already big due to less mobility. Then connecting 4 in series, consumes a lot of area and makes the gate slower.
Now in Dynamic logic, this p-chain is replaced by a single precharge transistor. The n-parallel combination is appended by a 'evaluate' N-transistor in series to the n-parallel combination, working on a clock.
The using 2 clocks normally called 'precharge' clock and 'evaluate' clock, the output of the gate is evaluated.
During the 'precharge' phase, the p tran is switched on, and the o/p of the gate is prechared to '1'. Then the appended 'evaluate' N-transistor is switched ON, to evaluate the final output of the gate.
Its advantages:
1. Faster
2. Smaller
Disadvantages:
1.Leakage current
2.multiple clocks needed.
Hope it helps
Kr,
Avi
http://www.vlsiip.com
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