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vidarson_qin
Joined: 31 Aug 2007
Posts: 2
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 05 Sep 2007 3:37 What's effect on max_fanout and max capacitance violation? |
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What's effect on max_fanout and max capacitance violation?
Currently,my design has no timing violation and max transition violation,but there are still 2 violations:max fanout and max capacitance violations on the system main clock, which I have set "dont_touch_network" properties on this clock path.
Must I fix these 2 violations?And how can I do that?
I need ur help,thanks in advance.
Best Regards,
Vidar
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sam536
Joined: 04 Jul 2007
Posts: 135
Helped: 14
Location: Tokyo
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| 05 Sep 2007 6:48 Re: What's effect on max_fanout and max capacitance violatio |
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Depends on which step in the flow. If you are working on logic synthesis, you dont need to fix on clock netowrk. Physical design tools works bettwer to build clock tree and optimizes for DRC violations too..
Hopefully your CTS will fix DRC on the clock lines..
Regards,
Sam
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quan228228
Joined: 23 Mar 2006
Posts: 214
Helped: 13
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| 05 Sep 2007 6:53 Re: What's effect on max_fanout and max capacitance violatio |
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set_ideal_net & set dont_touch_network together.
Generally, clock and reset are high fanout net which should be handled by backend tool.
David
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vidarson_qin
Joined: 31 Aug 2007
Posts: 2
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| 06 Sep 2007 7:19 What's effect on max_fanout and max capacitance violation? |
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hi,Sam:
Yes, I'm working on logic synthesis. So the physical design tools will fix the violations for me.
hi,David:
I have a try with both set_ideal_net & set dont_touch_network. It works! There is no violations! But I still compared the netlist with the previous one.I found there is nearly no difference between them. So is it to say that "set_ideal_net" on clock pin can only suppress the warnings:max_fanout and max_capacitance on the clock pin?
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Wenf.Yeh
Joined: 21 Aug 2007
Posts: 29
Helped: 2
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| 06 Sep 2007 17:29 What's effect on max_fanout and max capacitance violation? |
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hi ,vidarson_qin:
the max fanout is the number of cells (for example AND2)drived by output signals, here is the clock signal.
but the max cap equals to cap per cell * fanouts
so what's the problem? I think you can fix it quickly!
Regards,
Arthur
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