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cyteng
Joined: 06 Aug 2001
Posts: 33
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 09 Aug 2002 8:56 design compiler naming rule |
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After synthesis and optimization of my verilog file, I find some net( or wire) names is very strange. For example , the net connected from the output of nor gate to the data input of D flip-flop is called
" *cell*11/U2/control ". But I want very short net name like " N100" .
Does anyone know the answer to this question ?
Cyteng
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buzkiller
Joined: 01 Jan 1970
Posts: 91
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09 Aug 2002 9:11 design compiler naming rules |
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May be you should flatten your hierarchies.
regards,
Buzkiller.
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cuiyujie
Joined: 25 Apr 2002
Posts: 26
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11 Aug 2002 19:02 design compiler net name |
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| You cannot make sure all the name of all your internal wires is the same as before, adapt to these changes and don't count on post simulation a lot in verification.
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cdic
Joined: 28 Jun 2001
Posts: 155
Helped: 2
Location: silly valley
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11 Aug 2002 19:04 ungroup naming rule design compiler |
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| Change naming rule, eliminate *cell*, it's not fit for back-end design, also make sure no \ exist.
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magicball
Joined: 17 Feb 2002
Posts: 7
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11 Aug 2002 20:37 design compier changing cell names |
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| There are several articles in Solv*Net, the common solution is change names after synthesis.
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cyteng
Joined: 06 Aug 2001
Posts: 33
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12 Aug 2002 2:04 design compiler synthesis |
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If I would like to change the net name *cell*11/U2/CONTROL1 to NCONTROL1 , how do I write define_name_rulse command ?
I use "define_name_rules myrule -map {{"\*cell\*","U"}}",
but it maps "*cell*11/U2/CONTROL1" to "U".
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andromeda
Joined: 26 Sep 2002
Posts: 71
Helped: 1
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26 Sep 2002 22:11 09 dc compiler + define_name_rules |
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The simplest way is to use:
ungroup -flatten all -simple_names
(of course, if you want to remove the hierarchy)
Switch -simple_names will give you this type of names
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joe2moon
Joined: 19 Apr 2002
Posts: 389
Helped: 12
Location: MOON
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27 Sep 2002 8:23 design compiler change net name |
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I think you need to define the naming rule for "simple_names" before you can use it in change naming command 
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wllee
Joined: 26 Nov 2001
Posts: 37
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04 Dec 2002 4:42 synthesis bug |
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I hear DC2002.05 has bug in change naming rule function.
Maybe this is the bug.
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Google
AdSense
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04 Dec 2002 4:42 Ads |
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cnz
Joined: 10 Dec 2001
Posts: 125
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05 Dec 2002 13:31 how to use define_name_rules |
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| cdic wrote: |
| Change naming rule, eliminate *cell*, it's not fit for back-end design, also make sure no \ exist. |
I think that if you use cadence SE , we must eliminate "\".
however, to "*cell*" we needn't do it !
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cnz
Joined: 10 Dec 2001
Posts: 125
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05 Dec 2002 13:34 design compiler net names |
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define_name_rules BORG -allowed {A-Z a-z 0-9 _} \
-first_restricted {_ 0-9} \
-type cell
define_name_rules BORG -allowed {A-Z a-z 0-9 [ ] _} \
-first_restricted {_ 0-9} \
-type port
define_name_rules BORG -allowed {A-Z a-z 0-9 _} \
-first_restricted {_ 0-9} \
-type net
define_name_rules BORG -target_bus_naming_style {%s_%d} \
-type net
set bus_naming_style %s_%d
define_name_rules BORG -case_insensitive \
-map { {{"*cell*", "U"},{"*-return", "RET"}} }
change_names -hier -rule BORG
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