verilog simulation array to file conversion

EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> verilog simulation array to file conversion

Author

Message

zeeshanzia84

Joined: 29 May 2006
Posts: 202
Helped: 19
Location: Pakistan / Germany

27 Jul 2007 11:49 verilog simulation array to file conversion

Hi,

I have an array of vectors declared like (VERILOG):

reg [7:0] my_array[5000];

Afterwards, some data gets stored into this array as a result of some operations, done in a verilog simulation (i am using modelsim).

Is there any easy/direct way to save the contents of this array into a file say 'xyz.dat'??? Can someone give me some Verilog code or some code in some scripting language that ModelsimXE might support???

Thanks.

Google
AdSense
Google Adsense

27 Jul 2007 11:49 Ads

darylz

Joined: 24 Mar 2005
Posts: 132
Helped: 4

28 Jul 2007 2:20 verilog simulation array to file conversion

you can write a loop to dump it to a file. It will not take time longer than you posted this message.

sohiltri

Joined: 16 Dec 2006
Posts: 90
Helped: 5

28 Jul 2007 3:50 Re: verilog simulation array to file conversion

i wonder wil it store while simulating....loop can only store initial value....

but....If u are using 5000 cells ...than it is btter to use ram generator using some tools ehich vendor provides....this r IP cores....u can easily store info inside IP cores to any file u want (even externally)....make sure u hav requiored compiler...