How to use the define parameter of verilog in debussy?

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richardhuang

Joined: 26 May 2005
Posts: 43
Location: china

13 Jul 2007 4:21 verilog define parameter

in my verilog code, i use "ifdef **" to define some module, but how can i make debussy find the correct module ?how to tell debussy the define infomation?

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nand_gates

Joined: 19 Jul 2004
Posts: 907
Helped: 120

13 Jul 2007 6:38 debussy ifdef

Debussy understands `define You should include `defines in one file and pass
it to debussy!
Here is an example!
Debussy will show you OR gate

Code:

`define __OR 1
module alu(
// Outputs
y,
// Inputs
a, b
);
input a, b;
output y;

`ifdef __OR
assign y = a|b;
`else
assign y = a&b;
`endif
endmodule

Debussy will show you and gate!

Code:

module alu(
// Outputs
y,
// Inputs
a, b
);
input a, b;
output y;

`ifdef __OR
assign y = a|b;
`else
assign y = a&b;
`endif
endmodule


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How to use the define parameter of verilog in debussy?

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