how to split bus going to different blocks?

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mask_layout

Joined: 04 Apr 2006
Posts: 35

09 Jul 2007 8:20 verilog split bus

I have 3 blocks one with
output [31:0]
second block with input [8:0]
third block with input [31:9]

please help,

I want to connect the output pin to second and third block however

how to do it,...

wire [31:9] NETX;
wire [8:0] NETX;

will not work / conflicts.

Thanks,
mask_layout

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09 Jul 2007 8:20 Ads

verilog_always

Joined: 27 Dec 2006
Posts: 34
Helped: 2

09 Jul 2007 10:33 verilog bus split

Declare it as one vector
wire [31:0] netx and use [31:9]netx for one block and [8:0]netx for another block as input

deepakagarwal

Joined: 23 Nov 2006
Posts: 18

09 Jul 2007 12:45 how to splir a bus in vhdl

its depend s on HDL ... if you are using VHDL then you can use alias keyword...

for ex..
IR : std_logic_vector(18 downto 0)
and you want a variable rd1_erg which should be a part of IR from 11-13 then you can declare this as like

alias rd1_reg:reg_addr is IR(13 downto 11)

i think it will be helpful for you... if i helped you plz click on the help option.

thanks & regards
Deepak

mask_layout

Joined: 04 Apr 2006
Posts: 35

10 Jul 2007 9:19 how to split bus of wires in vhdl

thanks guys.. i dont really work on schematics and just trying to h(at)ck my verilog and this is confusing to me...

please let me know if i understand you correctly.

below are the relevant part of my verilog code problem:

Code:

module testcrap ( TCLOCK,TRESET,hapi, bdayo);

//-------------------
// Module I/O Signals
//-------------------
input TCLOCK, TRESET;
input [31:0] hapi;
output [15:0]bdayo;

wire [31:0] NETX;
wire [6:0] IN;
wire [15:0] pass;

//CONTROL BLOCK1
block1 block1 (
.CLK (TCLOCK),
.RST (TRESET),
.datab (NETX[8:0]), // this goes to ctrl block
.tr1 (IN[5:0]), // goes to block2
.tr2 (IN[6]) // goes to block2
);

//CONTROL BLOCK2
block2 block2 (
.CLK (TCLOCK),
.RST (TRESET),
.datab (NETX[31:9]), // connects to ctrl block
.in2 (IN), //connects to block1 IN[6:0]
.pass_o (pass) // connect to ctrl block
);

controlblock control (
.CLK (TCLOCK),
.RST (TRESET),
.hapi (hapi), //input
.out (bdayo), //output
.pasi (pass), // recives from blk2
.netx (NETX) //recieves from blk 1 &2
);

Please notice NETX comes from block1 and 2 and goes to one bus in control block.
Also block1 has tr1 and tr2 that goes to block2... also a bus joining bus... :(

Whats wrong or missing in my code?

Please help.. thanks in advance.

tkbits

Joined: 04 Dec 2004
Posts: 235
Helped: 36

10 Jul 2007 21:58 ver-149 design compiler

If you're still getting errors with NETX, make sure you have the correct bit ranges.

8:0 is 9 bits
31:9 is 23 bits

If the two inputs are 8- and 24-bits, the bit ranges are

7:0
31:8

mask_layout

Joined: 04 Apr 2006
Posts: 35

12 Jul 2007 4:37 verilog break bus

Thanks... Yup missed that bit ranges. thanks tkbits...
however, it looks like im doing some wrong sintax or grouping here...

In dc compiler im getting lots of errors on the code:

can some body help understand please

errors:
Symbol SLEPP not included in portlist (VER-149)
Base of subscript operator EVENT_NFO must be a vector(VER-194)
Illegal part select of memory 'EVENT_NFO'. (VER-963)

One problem i have is that it seems it wont take
ranges like
.datab (NETX[8:0]), // this goes to ctrl block
inside a block...

what is the right syntax for this?

I want to wire different signals from one block into a group of buswire in another block..

How do i do this?