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aswin123
Joined: 26 May 2007
Posts: 21
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 27 Jun 2007 19:43 Interface Block in System Verilog................. |
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What is the Importance of Interface Block In System Verilog........Without this we able to Build Environment or not......
what we can put into the interface block and how it will help to remaining blocks in the environment.....
Suggest me.
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boardlanguage
Joined: 06 Apr 2007
Posts: 96
Helped: 4
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27 Jun 2007 23:54 Re: Interface Block in System Verilog................. |
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| aswin123 wrote: |
| What is the Importance of Interface Block In System Verilog........Without this we able to Build Environment or not...... |
In Systemverilog, an 'interface' is a collection of signals (bit, wire, logic) and methods (functions, tasks.) You can use them to cutdown on the # single-name I/Os between modules. This can be helpful in large projects, where the large subsystems have hundreds of individual signals. (Use the 'interface' construct to group related bus-signals together.)
Since not too many people use Systemverilog for Design yet, I think interfaces are mostly used on the design verification (testbench) side. In summary, interfaces are a great convenience for testbench/verification engineers, because they can replace many wires with a single object (the interface).
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s8319
Joined: 08 Dec 2005
Posts: 25
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29 Jun 2007 9:54 Re: Interface Block in System Verilog................. |
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In Verilog, a module is the unit for any design entity.
SystemVerilog extends this to include other design entities such as an interface, a program block and, last but not the least, a clocking block.
An interface separates how a design interacts with the rest of the design from the design itself.
A program block separates a test benching function from a silicon implementable design.
And a clocking block specifies clock signals and the timing and synchronization requirements of various blocks. A clocking block is helpful in separating clocking activities of a design from its data assignments activities and can be used powerfully in test benching.
From: http://www.project-veripage.com/clocking_block_1.php
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calm
Joined: 17 Oct 2005
Posts: 264
Helped: 5
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01 Jul 2007 10:11 Interface Block in System Verilog................. |
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n Verilog, a module is the unit for any design entity.
SystemVerilog extends this to include other design entities such as an interface, a program block and, last but not the least, a clocking block.
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