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feel_on_on
Joined: 29 Apr 2005
Posts: 260
Helped: 1
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 25 Jun 2007 7:34 design compiler synthesis bottom up vs top down |
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example : a hierachical design A, top file : my_design.v
include two file : B.v and C.v
Question :
When synthesis , synthesis B.v and C.v individual,then....simply connect them on the top file mydesign.v?
or synthesis directly top file my_design.v ,then......? any suggestion is welcome.
If C.v have two asyn clock, only can synthesis B.v and C.v individually ?
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rameshsuthapalli
Joined: 27 Jun 2006
Posts: 163
Helped: 19
Location: bangalore,india
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25 Jun 2007 9:18 synthesis problem on Design Compiler |
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Hi,
The synthesis can be done in any way that described. But before that u have to check these things.
1)Is u r design is too big.
2)is there any asycronous paths present in between two design which require some sort of syncronization.
if u r design is too big to handle in one run then do the synthesis of diffrent modules seprately with some sort of care.and integrate them in the top and do the optimisation accross the bounady will solve the problem.
If u r design has syncronous paths where tool need's to take care of syncronisation and ur design is not too big then do the synthsis with top level constraints.other wise follow the previous solution.
regards,
ramesh.s
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25 Jun 2007 9:18 Ads |
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funster
Joined: 30 Jun 2005
Posts: 234
Helped: 12
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29 Jun 2007 7:59 Re: synthesis problem on Design Compiler |
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the first method is called bottom-up, the second method is called top-down,
if your design is not so large, always use the second method, it will give good
QOR(quality of result).
| feel_on_on wrote: |
example : a hierachical design A, top file : my_design.v
include two file : B.v and C.v
Question :
When synthesis , synthesis B.v and C.v individual,then....simply connect them on the top file mydesign.v?
or synthesis directly top file my_design.v ,then......? any suggestion is welcome.
If C.v have two asyn clock, only can synthesis B.v and C.v individually ? |
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| Back to top |
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FLEXcertifydll
Joined: 04 Sep 2003
Posts: 295
Helped: 3
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08 Jul 2007 8:09 synthesis problem on Design Compiler |
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for rapid timing closure, U can take bottom-up flow.
synthesis the sub-module firstly, then in top-level, set_dont_touch for the pre-synthesis module, and run synthesis.
It need more work for interface constraints.
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littlefield
Joined: 07 Jul 2007
Posts: 25
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08 Jul 2007 14:37 synthesis problem on Design Compiler |
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read the DC user guide
you will find the answer
search bottom-up , top-down,current_design
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