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combinatorial loop
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EDA_hg81



Joined: 25 Nov 2005
Posts: 395
Post19 Jun 2007 21:12   

combinatorial loop
I am using Xilinx ISE 9.1 to program Spartan3.

I got the following message : the following signal(s) form a combinatorial loop:

POL_TEMP.

What this means?

Thanks
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echo47



Joined: 07 Apr 2002
Posts: 4206
Helped: 566
Post20 Jun 2007 7:14   

the following signal(s) form a combinatorial loop
That warning message means your design has combinatorial logic with an output feeding back to the input, forming a loop. The result is usually a latch or oscillator. Most FPGA designers want to avoid such things, so the synthesis tool warns you.
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