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l-bert
Joined: 07 Jun 2007
Posts: 2
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 07 Jun 2007 12:00 ttl(74ls08) with the input of cmos(4017) and 555timer |
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one input of cmos(4017) and another input of 555timer to the 'and gate ttl(74ls08)'.
output of 'and gate' is connected to clock input of another cmos(4017). why the second cmos(4017) is also functioning eventhough the output of first cmos(4017) is low to the input of the 'and gate'?
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IanP
Joined: 05 Oct 2004
Posts: 6346
Helped: 1505
Location: West Coast
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| 07 Jun 2007 12:28 Re: ttl(74ls08) with the input of cmos(4017) and 555timer |
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If you have an AND gate and one of it's inputs is "L" there is no way the gate will allow to pass through signals from the other input(s), unless .. do you have bypass caps between each and every Vcc-GND pins ??? it has to be something of this nature ..
Regards,
IanP
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l-bert
Joined: 07 Jun 2007
Posts: 2
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| 07 Jun 2007 17:13 Re: ttl(74ls08) with the input of cmos(4017) and 555timer |
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| i didn't put any bypass caps. i suspect the output 'L' of ic 4017 to the input of 74ls08 is too high which the 74ls08 lies in the undefined states causing it to be detected as high. will this be the cause? the ic 4017 ouput '9' is actually connected to the clock enable itself(to stop counting) and to the input of ic 74ls08.
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