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negreponte
Joined: 26 Sep 2004
Posts: 94
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 24 May 2007 17:02 vcd problem please help |
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I am using design analyzer to execute my synthesys script.
The execution give me two files:
the sdf file and the verilog file.
I make a random simulation in modelsim to produce the vcd file.
Then I execute via prime power an other script which reads the verilog file and vcd
file
START OF FILE
#--------------------------------------------------------------------------
#The following is a template PrimePower TCL file for the VCD/Verilog flow.
# 1. Comments are denoted with "#".
# 2. Tool default values are provided. They can be modified.
# 3. Users must replace the term "fillin" with appropriate options/values.
# 4. Refer to the man pages for detailed command information.
#--------------------------------------------------------------------------
# Set Search Path / Library : (Can be placed in .pp_synopsys.setup)
#--------------------------------------------------------------------------
# set search_path /usr/eda/libraries/tsmc013/synopsys
set target_library /usr/eda/libraries/tsmc013/synopsys/typical.db
set link_library /usr/eda/libraries/tsmc013/synopsys/typical.db
#--------------------------------------------------------------------------
# Load Design and Activity Files
#--------------------------------------------------------------------------
read_verilog -hdl_compiler /home/xxxxxx/Desktop/Synopsys_scripts/sbox1.v
#read_verilog -hdl_compiler /root/our_core/tb.v
current_design sbox
#current_design tb
link
#read_vcd -strip_path tb/mux1inst /root/our_core/mux1.vcd
#read_vcd -strip_path /root/our_core/tb.v /root/our_core/mux1.vcd
read_vcd /home/*******/Desktop/Synopsys_scripts/sbox1.vcd
#--------------------------------------------------------------------------
# Apply Default Parameters
#--------------------------------------------------------------------------
set hierarchy_separator /
set_input_transition .1 [all_inputs]
#--------------------------------------------------------------------------
# Backannotation : Uncomment the commands which apply
#--------------------------------------------------------------------------
# set_wire_load_model -name fillin
# read_parasitics wire.spef
# current_instance fillin
# source fillin
#--------------------------------------------------------------------------
# Power Analysis and Waveform Generation
#--------------------------------------------------------------------------
#set_operating_conditions fillin
set_waveform_options -interval 1 -file vcd -format fsdb
calculate_power -waveform
report_power -file vcd -threshold 0 -sortby power
#--------------------------------------------------------------------------
# report capacitance
#--------------------------------------------------------------------------
#report_wire fillin
END OF FILE
When I execute the script via primepower I Have the following warnings
The netXXX cannot be covered by vcd file(.SIM-220)
about 300 warnings
I tried to change simulation senario but I had the some problems.
When I see the cells tha they contribute in dynamic power. only the cells that they are connected in the output of the circuit give dynamic power.
Any suggestions???
Last edited by negreponte on 22 Mar 2008 13:22; edited 1 time in total |
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roli
Joined: 29 Apr 2001
Posts: 947
Helped: 1
Location: 'SiliconWafer' Island
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| 12 Jul 2007 8:11 vcd problem please help |
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Which Simulator are you using ?
Try to expand all busses when creating the VCD file, including all Hierachies levels.
For example:
1. With Verilog-XL, use the '-x' option to expand busses
verilog -x <verilog files>
2. With 'ncsim', use the -expand option
ncvlog ...
ncelab -expand ...
ncsim ...
3. With 'ncverilog', use the +ncexpand option ncverilog +ncexpand ...
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kuppam
Joined: 15 May 2008
Posts: 2
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| 15 May 2008 10:28 Re: vcd problem please help |
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i am also getting same kind of issue and i am using prime time px tool...
I am getting below warning when i am reading a vcd file for calculating power estimation using pt px .
can anyone let me know whetehr wwe can ignore such kind of warnings or not
read_vcd -strip_path testbench ./vcd/tb.vcd
Warning: VCD header line 158627: redefining SAIF net name "Clk"
Warning: VCD header line 158628: redefining SAIF net name "adr[17]"
Warning: VCD header line 158628: redefining SAIF net name "adr[16]"
Warning: VCD header line 158628: redefining SAIF net name "Addr[15]"
Warning: VCD header line 158628: redefining SAIF net name "Addr[14]"
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flyjuju2
Joined: 24 Feb 2006
Posts: 6
Location: Stockholm and Lyon
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| 13 Aug 2008 12:44 Re: vcd problem please help |
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Hello !
I have exactly the same issue  . What is the cause, the consequence and how to get rid of those warnings ?
Thanks for any help,
Flyjuju
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santhosh007
Joined: 27 Aug 2008
Posts: 53
Helped: 15
Location: Bangalore
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| 28 Aug 2008 7:59 Re: vcd problem please help |
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| can you try to dump the VCD file using the VCS. Many times i have seen that the ncverilog vcd file is not rad by synopsys tools, bcoz the port definition are different in each tool
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