electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

USB 2.0 core
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> USB 2.0 core
Author Message
jenardo



Joined: 11 Jul 2006
Posts: 13
Location: Egypt
Post05 May 2007 17:57   

USB 2.0 core
Hi all,
In case of implementing a USB 2.0 core, I wanted to ask about its PHY interface.
1) Is it possible to output D+ and D- directly from the FPGA ?
2) or is some kind of transceiver in between needed to convert high and low voltages to a differential one ?
3) What is an UTMI interface ? and where exactly is it located in a design ?

Thanks
Back to top
nand_gates



Joined: 19 Jul 2004
Posts: 907
Helped: 120
Post07 May 2007 9:04   

Re: USB 2.0 core
For the UTMI refer to http://www.intel.com/technology/usb/download/2_0_Xcvr_Macrocell_1_05.pdf
Back to top
alzomor



Joined: 09 Jun 2005
Posts: 626
Helped: 31
Location: Cairo
Post07 May 2007 9:19   

Re: USB 2.0 core
Hi,

You need 1st to check USB2.0 specifications @
http://www.usb.org/developers

If you could meet the Phy specs @ D+ & D- using your FPGA , so you can use it for direct connection , but I don't think it's possible.

all designs use a PHY interface layer which is UTMI or ULPI.

Regarding the UTMI you can think of ULPI also which is simpler.

UTMI is USB 2.0 transceiver macrocell Interface.
and ULPI is a low Low PIN Interface version of UTMI.

Salam
Hossam Alzomor
www(dot)i-g(dot)org
Back to top
Google
AdSense
Google Adsense
Post07 May 2007 9:19   

Ads


Back to top
pini_1



Joined: 18 Jun 2007
Posts: 288
Helped: 17
Post18 Jun 2007 12:53   

Re: USB 2.0 core
I started to document a project which uses opencore's usb function IP. This IP can also work with USB 2.
I use for full speed devices. Presently the site is not complete, but you may take a look at http://bknpk.no-ip.biz.
Back to top
verma.ind



Joined: 05 Mar 2007
Posts: 24
Post04 Jul 2007 14:20   

Re: USB 2.0 core
For what purpose we will use chirp counter in USB2.0 core? Can any body help me?

Thanks
Back to top
gck



Joined: 17 Oct 2006
Posts: 149
Helped: 5
Post05 Jul 2007 5:55   

Re: USB 2.0 core
making D+ and D- sonnection by FPGA is not possible, for that i.e PHY layer chips are avilable u need to interface ur core with that.
Back to top
qasmi



Joined: 24 Apr 2004
Posts: 69
Helped: 2
Post09 Jul 2007 6:58   

USB 2.0 core
Is there any controller IC that interfaces with the PHY Layer Chip or USB Transceiver, instead of implementing the core in FPGA?
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> USB 2.0 core
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
USB 2.0 Host IP Core (1)
USB HID Core (3)
USB 2.0 core implementation on FPGA (1)
USB 2 IP core needed urgently (2)
regarding USB device core (2)
USB core on FPGA and Transceiver (1)
regarding USB device core development on FPGA (2)
REQ simple CPLD VHDL core for usb to 8 bit port (1)
which is numero uno --core duo & dual core processor (3)
the material of core for DN50 and PC40 Pot core (1)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS