fpga routing

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shahzad ahmad

Joined: 21 Dec 2004
Posts: 20
Helped: 12

20 Apr 2007 19:07 fpga routing

tellme about a tutorial on routing and plcement in xilinx ise8.2i

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banjo

Joined: 24 Dec 2005
Posts: 644
Helped: 118

21 Apr 2007 0:01 fpga routing

I do not know of any tutorials specifically about ISE8.2 PAR. The bottom line is you rarely need to worry about this. If you constrain your design properly, the tools will take can of place and route. The main constraint is the clock period constraint. With this piece of info and assuming that all clocks within the FPGA are derived from one input clock, then the compiler can handle everything to meet timing.

If you have multiple input clocks and signals cross clock domain boundaries, then the problem gets trickier. Sometimes you have to put placement constraints or delay constraints in the UCF file.

The other time that placement can be an issue is when the external pin assignments make internal routing difficult. If at all possible, do the FPGA design first and allow the Xilinx tools to dictate the pin assignments. It will optimize the assignments to make routing easier. If you have to fix the pin assignments before the design in order to fab the PCB is where it can get difficult.

echo47

Joined: 07 Apr 2002
Posts: 4206
Helped: 566

21 Apr 2007 1:29 fpga routing

In some situations, simple placement constraints can help PAR do a much better job. In one of my large Virtex-II projects, PAR couldn't meet my clock timing constraint because PAR was trying to route all my signal processing modules as one big mass of routes, resulting in numerous long routes with too much propagation delay. To solve the problem, I applied a simple LOC constraint to each HDL module, basically building a placement fence around each module. I arranged the regions so the data could flow between them without having to travel too far across the chip. PAR then completed the place/route in about one-third the time, and met my timing constraint.