doubt in system verilog

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deepu_s_s

Joined: 24 Mar 2007
Posts: 329
Helped: 13

17 Apr 2007 14:57 doubt in system verilog

can we synthesis using system verilog?

if so what is synthesis tool use for system verilog

aji_vlsi

Joined: 10 Sep 2004
Posts: 640
Helped: 72
Location: Bangalore, India

17 Apr 2007 15:51 Re: doubt in system verilog

deepu_s_s wrote:

can we synthesis using system verilog?

if so what is synthesis tool use for system verilog

Yes, there are several mini enhancements that are synthesiable and DC does allow them.. Some are:

always_comb, _ff etc.
unique/priority case/if
enumerated types
Interface

Not an exhaustive list above, but point is YES

Ajeetha, CVC
www.noveldv.com

deepu_s_s

Joined: 24 Mar 2007
Posts: 329
Helped: 13

17 Apr 2007 16:02 Re: doubt in system verilog

hi ajitha!

so can i use Synopsys DC as a synthesis tool for System verilog

shiv_emf

Joined: 31 Aug 2005
Posts: 641
Helped: 16

17 Apr 2007 17:01 doubt in system verilog

yes deepu U can use DC for synthesis
but few features(constructs) in system verilog cannot be synthesized !!.......

deepu_s_s

Joined: 24 Mar 2007
Posts: 329
Helped: 13

18 Apr 2007 6:03 Re: doubt in system verilog

hi shiv!

can u gimme some example features?

thx
deepu

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satyakumar

Joined: 18 May 2006
Posts: 186
Helped: 11
Location: Bangalore

18 Apr 2007 7:32 Re: doubt in system verilog

HI deepu,
The following features are not synthesizable.
1) unpacked unions
2) variable declarations in packages
3) static functions and tasks declared in packages
4) two state logic variables has some problem during synthesis

atuo

Joined: 19 Feb 2004
Posts: 59
Helped: 1

18 Apr 2007 11:40 Re: doubt in system verilog

deepu_s_s wrote:

can we synthesis using system verilog?

if so what is synthesis tool use for system verilog

Hi ,

I think the verilog-2001 is including in system verilog, so you can say we can use system verilog for synthesis.

But by now, system verilog is mainly used for HVL.

Thanks.

satyakumar

Joined: 18 May 2006
Posts: 186
Helped: 11
Location: Bangalore

18 Apr 2007 12:10 Re: doubt in system verilog

atuo wrote:

deepu_s_s wrote:

can we synthesis using system verilog?

if so what is synthesis tool use for system verilog

Hi ,

I think the verilog-2001 is including in system verilog, so you can say we can use system verilog for synthesis.

But by now, system verilog is mainly used for HVL.

Thanks.

I think there are lot enhancements to verilog-2001 in system verilog, its very comfortable at system level modeling. Regarding HVL its built in advantage of systemverilog.