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em1cr0nix



Joined: 17 Apr 2007
Posts: 7
Helped: 1
Post17 Apr 2007 2:11   As to Qs
Please help me provide the answers of the following.

How do you size NMOS and PMOS transistors to increase the threshold voltage?

Explain sizing of the inverter .

Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation.


Give the expression for calculating Delay in CMOS circuit.

Thanks in advance.

Regards,
Ronald
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strennor



Joined: 09 Dec 2003
Posts: 66
Helped: 13
Post17 Apr 2007 5:42   As to Qs
hi

for inverter threshold voltage, it depends on the size ratio of PMOS and NMOS
for delay, take a look at something like Logic Effort, maybe that's what you need
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