about low noise pmos buffer design

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about low noise pmos buffer design

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memsgg

Joined: 01 Aug 2005
Posts: 34
Helped: 1
Location: cambridge, UK

11 Apr 2007 22:33 about low noise pmos buffer design

I plan to design a low noise pmos buffer, which need large input and output swing rang, I have two topologies, can any one tell me which one is better? or any other topology is better than these two? Many thanks

1. I have a 5uA current already in my design, can I use 10X current mirror to bias the buffer? Is 50uA for bias buffer too low? How can I know how much buffer bias current is good?

2. can I use the topology (b)? just use a resistor to get the current? I think it may be not stable and may have more noise, is it?

Many thanks
Yong

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Last edited by memsgg on 12 Apr 2007 22:41; edited 1 time in total

acbalbason

Joined: 08 Apr 2007
Posts: 117
Helped: 10
Location: Chung Li, Taiwan

12 Apr 2007 18:58 Re: about low noise pmos buffer design

hi yong!

eventually you have to replace that ideal current source. either use a resistor or a diode connected transistor. it should act as a resistor. put an nmos and tie its drain to the gate. not unless you are not going to do the full layout?

- al

memsgg

Joined: 01 Aug 2005
Posts: 34
Helped: 1
Location: cambridge, UK

12 Apr 2007 22:36 Re: about low noise pmos buffer design

acbalbason wrote:

hi yong!

eventually you have to replace that ideal current source. either use a resistor or a diode connected transistor. it should act as a resistor. put an nmos and tie its drain to the gate. not unless you are not going to do the full layout?

- al

Do you mean I should choose the topology b? Can you please give me more explaination?

Yes I will do the full layout. I have a 5uA current already in the layout.

Thanks a lot.

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