electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

Available: Detailed RISC CPU IP Core Design Documentation
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> Available: Detailed RISC CPU IP Core Design Documentation
Author Message
JohnG300c



Joined: 05 Dec 2006
Posts: 91
Post10 Apr 2007 20:42   

Available: Detailed RISC CPU IP Core Design Documentation
Hello,

I have put up an article on our web site that describes a RISC CPU IP Core
that was created for one of our clients:
http://www.summitsoftconsulting.com/Pic10IpCore.htm

The RISC IP Core is instruction-compatible with the Microchip
PIC10F200-series of microcontrollers. Full design documentation is available
as well as full Verilog source code (including a full set of test benches).
This is a generic Controller-Datapath design that easily can be ported to VHDL.

I have attached the design document and the Verilog sources.

Thanks,
/John.

--------------------------------------------
John Gulbrandsen, Summit Soft Consulting
Professional Windows Systems Programming

26895 Aliso Creek Rd. Suite B504
Aliso Viejo, CA 92656-5301

Phone (877) 839-2543
Fax (877) 349-1818

John.Gulbrandsen (a t) SummitSoftConsulting (d o t) com
--------------------------------------------

Sorry, but you need login in to view this attachment
Back to top
GoodMan



Joined: 30 Sep 2002
Posts: 377
Post11 Apr 2007 2:04   

Re: Available: Detailed RISC CPU IP Core Design Documentatio
Hi,

Does this IP is free?
Back to top
Google
AdSense
Google Adsense
Post11 Apr 2007 2:04   

Ads


Back to top
JohnG300c



Joined: 05 Dec 2006
Posts: 91
Post11 Apr 2007 6:40   

Available: Detailed RISC CPU IP Core Design Documentation
Yes, the Verilog included can freely be used.

/John.

--------------------------------------------
John Gulbrandsen, Summit Soft Consulting
Professional Windows Systems Programming

26895 Aliso Creek Rd. Suite B504
Aliso Viejo, CA 92656-5301

Phone (877) 839-2543
Fax (877) 349-1818

John.Gulbrandsen (a t) SummitSoftConsulting (d o t) com
--------------------------------------------
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> Available: Detailed RISC CPU IP Core Design Documentation
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
CPU @ RTL Design - Verilog (with complete documentation) (24)
synthesize 16-bit RISC CPU (2)
Multi cycle instructions in a RISC CPU!! (3)
Please help me simulate CPU RISC! (2)
REQ: SystemC model for RISC CPU (3)
RISC CORE (5)
coldfire core - reques for detailed description (3)
A free RISC 51 vhdl Core (4)
I*EE 1394 Link Core and Documentation (3)
CPU Core RTL Verification (9)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS