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mary96960
Joined: 14 Mar 2007
Posts: 12
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 09 Apr 2007 10:41 Via size in layout |
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A rule in my D/R saying " (Vx sized by +0.095 μm/edge, then sized by -0.345 μm/edge) maximum width. ≤ 0.60". Anyone here understand what is this mean?
Thanks.
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leohart
Joined: 10 Nov 2006
Posts: 229
Helped: 12
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| 10 Apr 2007 2:29 Re: Via size in layout |
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and also what about this one?why add then substract same number?
①. (N/P MOS Vth) layer could be defined as below rule :
(a) {[(LVN)+(LVP)+(VDN)+(VDP)]+0.44um/side-0.44um/side}-0.44um/side+0.44um/side
(b) Define digitized area tone as “D(Dark)”.
N/P MOS Vth=Normal threshold voltage NMOS & PMOS channel implant
LVN=Low threshold voltage NMOS channel implant
LVP=Low threshold voltage PMOS channel implant
VDN=Depletion NMOS channel implant
VDP=Depletion PMOS channel implant
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Hughes
Joined: 10 Jun 2003
Posts: 712
Helped: 84
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| 10 Apr 2007 9:00 Re: Via size in layout |
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| leohart wrote: |
and also what about this one?why add then substract same number?
①. (N/P MOS Vth) layer could be defined as below rule :
(a) {[(LVN)+(LVP)+(VDN)+(VDP)]+0.44um/side-0.44um/side}-0.44um/side+0.44um/side
(b) Define digitized area tone as “D(Dark)”.
N/P MOS Vth=Normal threshold voltage NMOS & PMOS channel implant
LVN=Low threshold voltage NMOS channel implant
LVP=Low threshold voltage PMOS channel implant
VDN=Depletion NMOS channel implant
VDP=Depletion PMOS channel implant |
X + 0.44um / side - 0.44um / side
This action will fill narrow gaps (narrower than 0.88um) in layer X.
X - 0.44um / side + 0.44um / side
This action will remove narrow stripes in layer X
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leohart
Joined: 10 Nov 2006
Posts: 229
Helped: 12
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| 12 Apr 2007 5:45 Re: Via size in layout |
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| Hughes wrote: |
| leohart wrote: |
and also what about this one?why add then substract same number?
①. (N/P MOS Vth) layer could be defined as below rule :
(a) {[(LVN)+(LVP)+(VDN)+(VDP)]+0.44um/side-0.44um/side}-0.44um/side+0.44um/side
(b) Define digitized area tone as “D(Dark)”.
N/P MOS Vth=Normal threshold voltage NMOS & PMOS channel implant
LVN=Low threshold voltage NMOS channel implant
LVP=Low threshold voltage PMOS channel implant
VDN=Depletion NMOS channel implant
VDP=Depletion PMOS channel implant |
X + 0.44um / side - 0.44um / side
This action will fill narrow gaps (narrower than 0.88um) in layer X.
X - 0.44um / side + 0.44um / side
This action will remove narrow stripes in layer X |
THX!!
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