Elephantus
Joined: 11 Jul 2005
Posts: 31
Helped: 4
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 03 Apr 2007 13:17 outpktend |
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Hi all.
I am interfacing the Cypress EZ-USB FX2LP (Cy7C68013A) to a Lattice FPGA. The data is transferred from PC in AUTOOUT mode (auto-commit to peripheral domain) and the data is read from the USB chip through the slave FIFO interface.
Endpoint 2 is used, the fifo uses double buffering with packet size of 512 bytes. The external interface is set to 16 bits wide. The interface clock IFCLK is driven by the FPGA, and is inverted internally in the FX2 (through IFCONFIG setting). Clock frequency is 48 MHz. Initialization of the endpoint buffer is performed as directed by the example provided in the EZ-USB technical reference manual.
The observed behavior is that, when a 512-byte packet is sent to the USB chip, it is transferred to the peripheral domain and read by the FPGA. When the packet is read, the FX2 reports that the FIFO is empty. However, after a brief undetermined period of time (~ms), the FX2 de-asserts the FIFO empty flag on the EP2 fifo, although no data is sent from the PC to the endpoint buffer.
At that point reading EP2FIFOBCH:L reports that the FIFO contains 54 bytes of data, which was never explicitly sent to the usb endpoint by the PC. The FPGA promptly reads the phantom data from the FIFO, and the data appears to be random junk. Prior to the operation all of the FIFO buffers in EP2 were flushed by writing 0x82 to OUTPKTEND;
This condition repeats itself: After the FPGA reads the phantom data, after some time the empty flag is once again de-asserted and the FPGA reads 56 bytes again. This repeats over and over.
When I deactivated AUTOOUT mode and used explicit manual packet commit by FX2 firmware, this behavior was not observed.
Has anyone encountered problems like this before, and has he been able to solve them?
I would appreciate any help.
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