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andy2000a
Joined: 18 Jul 2001
Posts: 767
Helped: 7
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 20 Mar 2007 7:00 pmos ldo |
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I use 0.5u 18v cmos process
Io =30ma @ sink peak 1u ..
Io avg > 10m
if I use VIN =12 v vo=3.3 Nmos driver is easy design
even have dynamic loading transient
but when I use Vin=12 Vo > 5v ,
Nmos have Vth issue , vo <5v
, when I use pmos , pmos dynamic loading response is poor
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scottieman
Joined: 08 Aug 2005
Posts: 134
Helped: 11
Location: On Top of Silicon
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21 Mar 2007 6:25 ldo pmos and nmos |
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| andy2000a wrote: |
I use 0.5u 18v cmos process
Io =30ma @ sink peak 1u ..
Io avg > 10m
if I use VIN =12 v vo=3.3 Nmos driver is easy design
even have dynamic loading transient
but when I use Vin=12 Vo > 5v ,
Nmos have Vth issue , vo <5v
, when I use pmos , pmos dynamic loading response is poor |
You have good description on the tradeoffs. Still, what is your question?
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21 Mar 2007 6:25 Ads |
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andy2000a
Joined: 18 Jul 2001
Posts: 767
Helped: 7
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22 Mar 2007 4:02 output stage nmos |
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my question is , when I use pmos (nmos Vo <5v)
dynamic loading response too slow ..
when I use 100KHz pulse (drop 30ma) dymanic loading will cause 5v is drop .. even I put many nmos_Cap on 5v output is useless .. I am looking for "fast response" design for LDO .
my LDO is simple 2stage OPA driver a Pmos
I think maybe other pmos LDO design have skill
on fast response ..
by the way , is LDO i can not put too large Cap on die ..
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Btrend
Joined: 26 Dec 2003
Posts: 424
Helped: 55
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22 Mar 2007 6:54 cmos ldo design |
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| Quote: |
| when I use 100KHz pulse (drop 30ma) dymanic loading will cause 5v is drop |
if ur spec is 100KHz dymanic loading , ur BandWidth of LDO should be larger than 1Meg/(2*pi) to achieve 1% accuracy after loading released. simple 2stage will have larger gain than 1stage (diff-pair only), and larger gain means less speed.
so u can try use 1 stage with lower gain.
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