how to quantify MOS switch S/H linear settling error fo ADC?

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qslazio

Joined: 23 May 2004
Posts: 194
Helped: 9

15 Mar 2007 15:26 how to quantify MOS switch S/H linear settling error fo ADC?

Suppose the CMOS switch resistor and sampling capacitor is constant and driving voltage source is ideal. And this S/H is intended for ADC.

Then the only error source for CMOS switch sample-hold circuit is linear settling (let's just forget about charge injection or feedthrough).

As long as above conditions are true, linear settling only scales the input a little bit by (1-exp(-ts/tau)) "tau=1/(Ron × Csamp)". And it will not introduce distortion or increase noise level. It only scales the signal gain a little bit.

My question is how is this linear settling error related with S/H or ADC's ENOB or Resolution. As we know ADC's ENOB is related with SNR which can be determined by FFT analysis.

But when we do the sampled voltage's FFT with linear settling error. It seems that it will not alter the result of SNR very much because no extra noise/distortion is added and it only scales the input a little bit.

I'm asking this because now I'm optimizing an cmos sampling switch for sigma-delta ADC with FFT analysis. Because I want to reduce charge injection indeced distortion. I have to reduce switch size. I want to know how small can I go for safety.

Anyone please help me!
Thank you very much.

gingerjiang

Joined: 01 Mar 2006
Posts: 212
Helped: 11

16 Mar 2007 2:23 Re: how to quantify MOS switch S/H linear settling error fo

for the performance of ADC don't be degraded, the S/H circuit need to settle to the whole resolution of ADC, so the settling error exp(-ts/tau) should be less than LSB/2 of ADC
to reduce the charge injection effect, only decreasing the switch size isn't enough. for reduce this effect, use full differential architecture and bottom plane sampling technique.
set the switch size to ensure the sampling error of sampling phase within the whole resolution.
good luck

qslazio

Joined: 23 May 2004
Posts: 194
Helped: 9

16 Mar 2007 2:48 Re: how to quantify MOS switch S/H linear settling error fo

thanks for reply.
intuitively I agree with you that the S/H should settle within the ADC's resolution.
But I'm just assume linear settling error only scales the input without adding noise, am I right? If this is right, SNR will only drop by 20*log(0.99)≈0.0873dB (assume 1% linear settling error), this error should be negligible.

gingerjiang

Joined: 01 Mar 2006
Posts: 212
Helped: 11

16 Mar 2007 4:14 Re: how to quantify MOS switch S/H linear settling error fo

well, now i think your opinion is reasonable in S/H circuit at least
scaling the input only reduces the signal swing, i.e. dynamic range, this effect is negligible
wait for other opinion

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qslazio

Joined: 23 May 2004
Posts: 194
Helped: 9

27 Mar 2007 15:49 how to quantify MOS switch S/H linear settling error fo ADC?

Is there anyone can help me? Please give your comment.
Thanks again!

maxwellequ

Joined: 27 Jun 2001
Posts: 185
Helped: 11

27 Mar 2007 19:07 Re: how to quantify MOS switch S/H linear settling error fo

Dear qslazio,

What you say is true if the sampling capacitors are discharged in the hold phase of the S/H, which is most probably your case (if the previous sampled value remained stored in the capacitors then you would have a low pass filter characteristic, but still no distortion).

The problem is that the effects that you're wanting to ignore (non-linear switch resistance, non-linear parasitic capacitances of the switch transistors which must also be charged) will transform this "gain error" into non-linearity.... So, at the end, the best is to guarantee a "complete" settling (i.e. negligible difference between real and ideal sampled value).

Regards.

PS: For example if you assume that the settling of the S/H amplifier is linear then you would not have to ensure a "complete settling" because, again, you would only have a gain error. The problem is to ensure that the amplifier has a linear settling .....

Btrend

Joined: 26 Dec 2003
Posts: 424
Helped: 55

28 Mar 2007 10:33 Re: how to quantify MOS switch S/H linear settling error fo

qslazio wrote:

thanks for reply.
But I'm just assume linear settling error only scales the input without adding noise, am I right? If this is right, SNR will only drop by 20*log(0.99)≈0.0873dB (assume 1% linear settling error), this error should be negligible.

In my opinion,
1. if 1% linear settling error is applied to all level of input signal, then these error are signal depent: ΔVmax=Vin_max*exp(-t/τ)=Vin_max*0.01=(2^N)VLSB*0.01
i.e. ur noise will be larger if input amplitude is larger.
2. if 1% linear settling error is applied to 1LSB, then these error is constant
ΔV=Vin*exp(-t/τ)=VLSB*0.01
3. if (1) is true then ur SNR will degrade by N*0.303+0.09dB, also THD will be worse
4. if (2) is true then ur SNR will degrade by 0.09dB, as u had stated