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feel_on_on
Joined: 29 Apr 2005
Posts: 244
Helped: 1
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 13 Mar 2007 10:40 question on DC |
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CLK1,CLK2,CLK3 was selected by a multiplex,then generate CLK4,CLK4 frequency was divided ,and get CLK5,.....
how to constraint the design clock with Design Compiler
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sree205
Joined: 13 Mar 2006
Posts: 418
Helped: 30
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| 13 Mar 2007 11:17 question on DC |
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| u can look up these commands : create clock and set_propagated_clock.
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moorehuang
Joined: 12 Mar 2007
Posts: 5
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| 14 Mar 2007 3:49 question on DC |
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| CLK5 should be set as generated_clock
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rsrinivas
Joined: 10 Oct 2006
Posts: 418
Helped: 36
Location: bengalooru
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| 14 Mar 2007 6:42 question on DC |
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clk4 should be gated clk
and as previously said clk5 is generated clk
u can use create_generated_clk command and give the divide factor.
u can see the generated clk after synthesis in ur report from report_clk command
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sumit_techkgp
Joined: 01 Apr 2007
Posts: 135
Helped: 3
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| 14 Apr 2007 7:33 question on DC |
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| Propagate the clock
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