[DC] Determine parameter in set_input_delay?

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davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

26 Feb 2007 9:26 [DC] Determine parameter in set_input_delay?

Hi all,

When use set_input_delay/set_output_delay, how to determine the -max/-min parameter? Is it calculated by hand , calculated by tools, or give out by some standard specification?

Code:

set_input_delay -max 498 -clock EXTSCL [find port ddc_sda_i]
set_input_delay -min 0 -clock EXTSCL [find port ddc_sda_i]

set_output_delay -max 498 -clock CLK1MHZ [find port ddc_sda_o]
set_output_delay -min 0 -clock CLK1MHZ [find port ddc_sda_o]

Best regards,
Davy

megastar007

Joined: 20 Feb 2007
Posts: 82
Helped: 5
Location: Munich

26 Feb 2007 15:24 Re: [DC] Determine parameter in set_input_delay?

General concept is to use time budgeting. 40% of clock period is used as input and output delays

davyzhu

Joined: 23 May 2004
Posts: 521
Helped: 3
Location: oriental

27 Feb 2007 1:53 [DC] Determine parameter in set_input_delay?

Hi Megastar007,

Thanks, so the delay is calculated by hand, is it right?

Best regards,
Davy

yln2k2

Joined: 22 Sep 2006
Posts: 89
Helped: 10

27 Feb 2007 2:27 Re: [DC] Determine parameter in set_input_delay?

Hi ,

This should be as a part of specification .
In general if you are doing synthesis of module you do 40% of clk . But if you constrain the same at SOC you need to go through data sheet and get the same .

Thanks & Regards
yln

cnspy

Joined: 10 Sep 2002
Posts: 155
Helped: 3

27 Feb 2007 3:39 [DC] Determine parameter in set_input_delay?

I think we should estimate the outside environment for the chip to give the input delay value. I am right?

gong.kidd

Joined: 24 Oct 2006
Posts: 19
Helped: 2

27 Feb 2007 6:56 Re: [DC] Determine parameter in set_input_delay?

If u synthesize modules which is nothing without outer environment, that use 40% clock period; if else, should refer datasheet of outer chip.

sameer_dlh25

Joined: 21 Sep 2005
Posts: 85
Helped: 13
Location: Bangalore India

27 Feb 2007 11:21 Re: [DC] Determine parameter in set_input_delay?

Hi davyzhu,

It is totally dependent on the environment where your design is going to sit.

For example if your input is driven by a block/chip which is fast enough to give the output in 20% time
then your design budget is 80% of clock period.

For a block level or IP design these margins are specified by the architect whereas at chip level this
is driven by a application requirements. Neutral