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Elnegm
Joined: 28 Jun 2005
Posts: 34
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 21 Feb 2007 15:46 Long time Synthesis in ISE |
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I'm using FPGA Xilix virtex 2 pro FG45 and Xilinx ISE
The problem that ISE when i Synthesis my verilog core which is 8051 it continue Synthesis,it Synthesis for along time and didn't fiinsh,the module that ISE still Synthesis and didn't fininsh is the ROM,so i can't Synthesis the core ,Any solutions?
Thanks in advance
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vlsi_whiz
Joined: 12 Nov 2005
Posts: 171
Helped: 24
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26 Feb 2007 3:59 Re: Long time Synthesis in ISE |
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| This can occur if your design has large RAM or ROM blocks. The ISE tool tries to breakdown the ROM/RAM logic and implement it. This will take longer time and may cause the tool to hang. A better option for you is to use the built-in RAM/ROM blocks in Xilinx for your core's RAM/ROM. This will force Xilinx to skip synthesis of the RAM/ROM and directly instantiate the built-in RAM/ROM.
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s3034585
Joined: 24 May 2004
Posts: 226
Helped: 1
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26 Feb 2007 8:12 Re: Long time Synthesis in ISE |
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| If you have implement the RAM/ROM then ISE will take a long time to synthesis it. The best way to do is the use built in block rams... rather than implementing them....
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