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NoHa111
Joined: 02 Sep 2005
Posts: 31
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 19 Feb 2007 11:35 STATE MACHINE |
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Hi all,
please i have a problem in writing a code for simple state machine on xilinix
this is the code and the errors always appear in process2 at every (when) it just says that (unexpected when,expected end)!!!!
here is the code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bass2 is
Port ( wp : out STD_LOGIC_VECTOR (11 downto 0);
wz : out STD_LOGIC_VECTOR (11 downto 0);
bup : in STD_LOGIC;
bdn : in STD_LOGIC);
end bass2;
architecture Behavioral of bass2 is
type state_type is (flat, six, twelve, nsix, ntwelve);
signal state, next_state: state_type;
begin
process1: process (bup, bdn)
begin
if (bup ='0' and bdn='0') then
state <= flat;
elsif (bup = '1' or bdn='1') then
state <= next_state;
end if;
end process process1;
process2 : process (bup, bdn)
begin
case state is
when flat =>
if (bup = '1' and bdn='0') then
next_state <= six;
else if (bup = '0' and bdn='1') then
next_state <= nsix;
end if;
when six =>
if (bup = '1' and bdn='0') then
next_state <= twelve;
else if (bup = '0' and bdn='1') then
next_state <= flat;
end if;
when twelve =>
if (bup = '1' and bdn='0') then
next_state <= twelve;
else if (bup = '0' and bdn='1') then
next_state <= six;
end if;
when nsix =>
if (bup = '1' and bdn='0') then
next_state <= flat;
else if (bup = '0' and bdn='1') then
next_state <= ntwelve;
end if;
when ntwelve =>
if (bup = '1' and bdn='0') then
next_state <= nsix;
else if (bup = '0' and bdn='1') then
next_state <= ntwelve;
end if;
end case;
end process process2;
process3 : process (state)
begin
case state is
when flat => wp <= "011000100001";
when six => wp <= "011000100001";
when twelve => wp <= "011000100001";
when nsix => wp <= "011000011111";
when ntwelve => wp <= "110000110111";
end case;
end process process3;
end Behavioral;
sorry if it seems silly but i am a bigginer (really it is my first code:D)
please i need your help urgently and ASAP
THANKS ALOT IN ADVANCE
NOHA
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nand_gates
Joined: 19 Jul 2004
Posts: 907
Helped: 120
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19 Feb 2007 12:44 Re: STATE MACHINE |
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Check out this!
| Code: |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bass2 is
port ( wp : out std_logic_vector (11 downto 0);
wz : out std_logic_vector (11 downto 0);
bup : in std_logic;
bdn : in std_logic);
end bass2;
architecture Behavioral of bass2 is
type state_type is (flat, six, twelve, nsix, ntwelve);
signal state, next_state : state_type;
begin
process1 : process (bup, bdn)
begin
if (bup = '0' and bdn = '0') then
state <= flat;
elsif (bup = '1' or bdn = '1') then
state <= next_state;
end if;
end process process1;
process2 : process (bup, bdn)
begin
case state is
when flat =>
if (bup = '1' and bdn = '0') then
next_state <= six;
elsif (bup = '0' and bdn = '1') then
next_state <= nsix;
end if;
when six =>
if (bup = '1' and bdn = '0') then
next_state <= twelve;
elsif (bup = '0' and bdn = '1') then
next_state <= flat;
end if;
when twelve =>
if (bup = '1' and bdn = '0') then
next_state <= twelve;
elsif (bup = '0' and bdn = '1') then
next_state <= six;
end if;
when nsix =>
if (bup = '1' and bdn = '0') then
next_state <= flat;
elsif (bup = '0' and bdn = '1') then
next_state <= ntwelve;
end if;
when ntwelve =>
if (bup = '1' and bdn = '0') then
next_state <= nsix;
elsif (bup = '0' and bdn = '1') then
next_state <= ntwelve;
end if;
end case;
end process process2;
process3 : process (state)
begin
case state is
when flat => wp <= "011000100001";
when six => wp <= "011000100001";
when twelve => wp <= "011000100001";
when nsix => wp <= "011000011111";
when ntwelve => wp <= "110000110111";
end case;
end process process3;
end Behavioral; |
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19 Feb 2007 12:44 Ads |
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NoHa111
Joined: 02 Sep 2005
Posts: 31
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19 Feb 2007 14:53 Re: STATE MACHINE |
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THANKS alot for your help
now it works prperly:D
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salma ali bakr
Joined: 27 Jan 2006
Posts: 973
Helped: 80
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19 Feb 2007 14:56 Re: STATE MACHINE |
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salamo alikom noha,
u just need to replace the ELSE IF by ELSIF
it's just one word
cause if it's ELSE IF, then u wrote two IF but only one end
do u get it ?
good luck,
Salma:)
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