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omara007
Joined: 06 Jan 2003
Posts: 1147
Helped: 35
Location: Dubai
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 09 Feb 2007 12:44 Can I use this Verilog style inside VHDL ? |
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Hi guys ..
Is it allowed to use the verilog style of representing values like :
x = 32'b0
in VHDL ?
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Guru59
Joined: 10 Jul 2006
Posts: 232
Helped: 4
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| 09 Feb 2007 13:22 Re: Can I use this Verilog style inside VHDL ? |
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No you have to use as
x = "0000000000000000000000000000000"
I think...............correct me if i am wrong
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omara007
Joined: 06 Jan 2003
Posts: 1147
Helped: 35
Location: Dubai
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| 09 Feb 2007 14:30 Re: Can I use this Verilog style inside VHDL ? |
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| Guru59 wrote: |
No you have to use as
x = "0000000000000000000000000000000"
I think...............correct me if i am wrong |
This is the normal way .. but sometimes u may have very large buses and it's not easy to assign the values to them this way ..
I once saw some vhdl code like this :
x = 16#0#
Anyone tried that style before ? .. I tried it with 32#0# but it didn't work !! dunno what was the problem !!!
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khaila
Joined: 14 Jan 2007
Posts: 116
Helped: 4
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| 09 Feb 2007 16:44 Re: Can I use this Verilog style inside VHDL ? |
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sure not.
but in VHDL you may use:
x <= (other => '0');
I think it is smartest that Verilog while there is no need to declire the lenght/width!!
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aji_vlsi
Joined: 10 Sep 2004
Posts: 593
Helped: 69
Location: Bangalore, India
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| 09 Feb 2007 18:19 Re: Can I use this Verilog style inside VHDL ? |
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| khaila wrote: |
sure not.
but in VHDL you may use:
x <= (other => '0');
I think it is smartest that Verilog while there is no need to declire the lenght/width!! |
In SystemVerilog you have unsized 'b that takes care of this length/width:
x <= 'b0; // No SIZE specification
HTH
Ajeetha, CVC
www.noveldv.com
Added after 2 minutes:
| omara007 wrote: |
[
This is the normal way .. but sometimes u may have very large buses and it's not easy to assign the values to them this way ..
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There are array aggregates that let you do this nicely in VHDL. Take a look at VHDL FAQ at www.vhdl.org/comp.lang.vhdl
| Quote: |
I once saw some vhdl code like this :
x = 16#0#
Anyone tried that style before ? .. I tried it with 32#0# but it didn't work !! dunno what was the problem !!!
|
I've used it, it works fine. IIRC, this was added in VHDL 93, maybe your tool has a flag for V93 and you didn't turn it on?
Regards
Ajeetha, CVC
www.noveldv.com
Last edited by aji_vlsi on 09 Feb 2007 18:31; edited 1 time in total |
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omara007
Joined: 06 Jan 2003
Posts: 1147
Helped: 35
Location: Dubai
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| 09 Feb 2007 18:29 Re: Can I use this Verilog style inside VHDL ? |
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| khaila wrote: |
sure not.
but in VHDL you may use:
x <= (other => '0');
I think it is smartest that Verilog while there is no need to declire the lenght/width!! |
this won't work with a value of 23 for example .. it only works if u want to load x with all zeros ..
Added after 1 minutes:
| aji_vlsi wrote: |
| khaila wrote: |
sure not.
but in VHDL you may use:
x <= (other => '0');
I think it is smartest that Verilog while there is no need to declire the lenght/width!! |
In SystemVerilog you have unsized 'b that takes care of this length/width:
x <= 'b0; // No SIZE specification
HTH
Ajeetha, CVC
www.noveldv.com
Added after 2 minutes:
| omara007 wrote: |
[
This is the normal way .. but sometimes u may have very large buses and it's not easy to assign the values to them this way ..
|
There are array aggregates that let you do this nicely in VHDL. Take a look at VHDL FAQ at www.vhdl.org/comp.lang.vhdl
I once saw some vhdl code like this :
x = 16#0#
Anyone tried that style before ? .. I tried it with 32#0# but it didn't work !! dunno what was the problem !!!
I've used it, it works fine. IIRC, this was added in VHDL 93, maybe your tool has a flag for V93 and you didn't turn it on?
Regards
Ajeetha, CVC
www.noveldv.com |
Does 32#0# mean 32 zeros or a zero based on a 32 digits numbering system ? .. (for sure there is no 32 base for a numbering system) ..
I have indeed switched on the VHDL 93 compliant compilation .. (-v93 in Cadence NC)... but still I'm getting this error :
based literal base out of bounds [13.4.2].
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