A problem on PLI for Verilog

EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)

Author

Message

eruisi

Joined: 03 Jan 2006
Posts: 94
Helped: 15
Location: MA

08 Feb 2007 17:58 A problem on PLI for Verilog

I am using PLI1.0 for NCVerilog in a simple design but getting some errors.

Here is my PLI function in C:

Code:

int my_timing()
{
handle gate;
double new_rise, new_fall;

acc_initialize();
acc_configure(accToHiZDelay, "max");
gate = acc_handle_tfarg(1);

acc_fetch_delays(gate, &new_rise, &new_fall);
io_printf("Gate %s old delay: rise-%f, fall-%f\n", acc_fetch_fullname(gate), new_rise,new_fall);

new_rise = acc_fetch_tfarg(2);
new_fall = acc_fetch_tfarg(3);
acc_replace_delays(gate, new_rise, new_fall);
acc_fetch_delays(gate, &new_rise, &new_fall);
io_printf("Gate %s new delay: rise-%f, fall-%f\n", acc_fetch_fullname(gate), new_rise,new_fall);
acc_close();

}

but I got the following mssages in my NCverilog simulation:

ncsim> run
ERROR: ACC AGPDNMP
Getting primitive delay information has not been implemented yet.
./top.v, 10: $my_timing(nd1,0.100000,0.100000)
Gate nand4.nd1 old delay: rise-0.000000, fall-0.000000
ERROR: ACC APPDNMP
Annotating primitive delays has not been implemented yet.
./top.v, 10: $my_timing(nd1,0.100000,0.100000)
ERROR: ACC AGPDNMP
Getting primitive delay information has not been implemented yet.
./top.v, 10: $my_timing(nd1,0.100000,0.100000)
Gate nand4.nd1 new delay: rise-0.100000, fall-0.100000
ncsim: *W,RNQUIE: Simulation is complete.

It seems to me the gate delay has been updated with new value but why there are error messages for acc_fetch_delays() and acc_replace_delays()?

I did include -ANNO_SIMTIME option in ncelab command line

Thanks for your kindly help!

aji_vlsi

Joined: 10 Sep 2004
Posts: 593
Helped: 69
Location: Bangalore, India

08 Feb 2007 19:25 Re: A problem on PLI for Verilog

I would trust the error saying "not implemented yet" - why do you believe it still works? Do you have waveform or some other proof? Your best bet is to contact CDN support as it may be available in newer release.

Also, try porting it to VPI, that is the way going forward, ACC/TF is way too old (though little faster than VPI)

Regards
Ajeetha, CVC
www.noveldv.com

eruisi

Joined: 03 Jan 2006
Posts: 94
Helped: 15
Location: MA

08 Feb 2007 19:49 Re: A problem on PLI for Verilog

The new delays are printed based on the values I feteched from the simulator.

Code:

acc_replace_delays(gate, new_rise, new_fall);
acc_fetch_delays(gate, &new_rise, &new_fall);
io_printf("Gate %s new delay: rise-%f, fall-%f\n", acc_fetch_fullname(gate), new_rise,new_fall);

Is this right?

aji_vlsi wrote:

eruisi

Joined: 03 Jan 2006
Posts: 94
Helped: 15
Location: MA

09 Feb 2007 3:29 Re: A problem on PLI for Verilog

I run a testbench and found that the gate delays are not impacted.
Did I use acc_replace_delays() in the wrong way or it's not implemented in ldv4?
It's quite wierd to me because I was following the examples in cdsdoc of ldv4.

Can anyone help me out?

Here is the verilog code:

Code:

`timescale 1ns/100ps
module nand4(d1, d2, d3, d4, out);
input d1, d2, d3, d4;
output out;

wire out1, out2;
nand nd1(out1, d1, d2);
nand nd2(out2, d3, d4);
nand nd3(out, out1, out2);
endmodule

module nand4_tb();
reg w1, w2, w3, w4;
wire out;

nand4 dut(.d1(w1), .d2(w2), .d3(w3), .d4(w4), .out(out));

initial begin
   w1=0; w2=0; w3=1; w4=0;
   #10 w1=0; w2=0; w3=1; w4=1;
   #20 $finish;
end

initial begin
$fsdbDumpfile("top.fsdb");
$fsdbDumpvars(0, dut);
end

initial $my_timing(nand4_tb.dut.nd2, 10, 10);
endmodule

aji_vlsi

Joined: 10 Sep 2004
Posts: 593
Helped: 69
Location: Bangalore, India

09 Feb 2007 3:40 Re: A problem on PLI for Verilog

eruisi wrote:

I run a testbench and found that the gate delays are not impacted.
Did I use acc_replace_delays() in the wrong way?

I don't believe so, looks more like this is a tool side issue of "not yet done". Do you have expected/golden log that you can provide? As you can appreciate, it is hard for a 3rd party to analyze it in great detail your testcase, and having a golden reference from you can help. In that case I can try with other simulator and see if we get different results.

Quote:

Can anyone help me out?

If this is in production code you are better off contacting CDN support. If it is rather experimental code, someone in the forum can help. Also try posting to comp.lang.verilog

Regards
Ajeetha, CVC
www.noveldv.com

EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)

Page 1 of 1

All times are GMT + 1 Hour

Abuse
Administrator
Moderators

sitemap