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subramanyam
Joined: 29 Jul 2006
Posts: 67
Helped: 4
Location: hyderabad
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 07 Feb 2007 13:38 slow to fast clock domain .... is an asynch. fifo needed ??? |
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Hii ,
Is it really needed a FIFO while synchronizing a slow clock to a fast clock ??If it is fast to slow u should have a FIFO as we have to store the data. What about slow to fast case ?? As any way there is no need to have more than 1 or 2 locations in the FIFO as fast clock can read data immediately . What is the approach usually they follow in the industry??
I am a lot confused regarding this slow to fast and fast to slow clock domains and plz don't make me to furthur confuse by just posting to make points . I request
people who is having experience on this or who has really worked on this to post the reply.
best regards,
subbu.
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servicemann
Joined: 20 Jan 2006
Posts: 189
Helped: 13
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| 07 Feb 2007 14:30 slow to fast clock domain .... is an asynch. fifo needed ??? |
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What do you mean with fast and slow clocks?
Do they have the same frequency - just phase shift?
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kbulusu
Joined: 23 Apr 2003
Posts: 122
Helped: 7
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| 07 Feb 2007 20:45 Re: slow to fast clock domain .... is an asynch. fifo needed |
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I'm not sure what you are looking for exactly ? already do you have a synchronizer in place or you asking how to supress the glitches etc
u still need syncronizer as ur data will be active for more than 1 clock cycle in fast clock domain.u need some sort of synchronizer which works on edge detection. U need to check for both the rising edge and the duration .
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khaila
Joined: 14 Jan 2007
Posts: 116
Helped: 4
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| 07 Feb 2007 23:49 Re: slow to fast clock domain .... is an asynch. fifo needed |
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| subramanyam wrote: |
Hii ,
Is it really needed a FIFO while synchronizing a slow clock to a fast clock ??If it is fast to slow u should have a FIFO as we have to store the data. What about slow to fast case ?? As any way there is no need to have more than 1 or 2 locations in the FIFO as fast clock can read data immediately . What is the approach usually they follow in the industry??
I am a lot confused regarding this slow to fast and fast to slow clock domains and plz don't make me to furthur confuse by just posting to make points . I request
people who is having experience on this or who has really worked on this to post the reply.
best regards,
subbu. |
In the case that you described you don't need any FIFO.
But
You should make two important things:
1. Synchronize the data from slow-rate domain by TWO flip-flops.
2. You should take care for the control signal such as WR to be widened in order to match the rates of the slow-rate domain.
that's all.
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s3034585
Joined: 24 May 2004
Posts: 213
Helped: 1
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| 08 Feb 2007 10:02 Re: slow to fast clock domain .... is an asynch. fifo needed |
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Hi
for synchornising data from Slow to Fast you dnt need a fifo... data can be synchoronised using 2 ff clked by fast clk.. control signals also can be done in the same manner....
there is a lot of material on this in this and fpga forum.
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