Scan chain with neg edge and pos edge flops

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shahal

Joined: 11 Jan 2007
Posts: 50

06 Feb 2007 4:44 lockup latches

You have a scan chain with negative edge flops and positive edged flops. In the chain, which should come first and why?

kbulusu

Joined: 23 Apr 2003
Posts: 133
Helped: 7

06 Feb 2007 7:37 lockup latch waveform

if you dont have any design restrictions of combining the diff edges, you can configure the DFT tool to combine both of them and it will take of the ordering/partitioning/balancing etc . But if you want to understand theoritically , I wont give you the entire answer, but try to think in terms of timing violations (hold time violations etc )...it will answer your questions.

udit

Joined: 27 Jun 2005
Posts: 84
Helped: 2
Location: Canada

07 Feb 2007 9:05 scan chain negativ edge clocked

I have heard that you should always place the neg edge flipflops first and then the pos edge flipflops in a scan chain. But I am not aware of the reason.

dr_dft

Joined: 10 Aug 2005
Posts: 87
Helped: 1

08 Feb 2007 7:03 why add lockup latch end scan chain

Depends on your clock waveform. If your clock waveform is return-to-zero (0->1->0), then negedge should be first. If your clock is return-to-one (1->0->1), then posedge should be first.
The reason is because you don't want a scan data to hop across 2 flip-flops with a single clock pulse, which means those 2 flip-flops will always end up with the same scan-in data.
For example, if your clock is 0->1->0 and your chain is as follows:
ScanIn -> FF1(pos) -> FF2(neg) -> ScanOut
whatever we put into ScanIn will appear at ScanOut after one clock pulse (posedge clock followed by negedge pulse). However, if the chain is as follows,
ScanIn -> FF1(neg) -> FF2(pos) -> ScanOut
then the posedge clock will update FF2 (using data stored in FF1), then afterwards the negedge will update FF1 (using ScanIn).

shahal

Joined: 11 Jan 2007
Posts: 50

09 Feb 2007 6:06 timing path from flop to latch

Dr Dft, let me ask a question. Lock up latches, ofcourse you use it to cross clock domain boundry. Would you use lock up Latches between adjacent flops if the clock was skew between the two flop clocks was greater than the data propagation path between the flops?

My understanding is yes you would, given the above criteria because the second flop will latch the new value of the first flop. Is my understanding correct or is this some how tool dependent and some tools will insert LLs and some wont?

dr_dft

Joined: 10 Aug 2005
Posts: 87
Helped: 1

09 Feb 2007 6:23 scan edge

shalal,
Almost all scan insertion tools that I know of don't have any information about delays or clock skews, so scan insertion tools will not insert data lockup latches if it they are clock by the same clock source.
If the skew is small, then you should leave it to the backend tool to fix the hold time violation (by adding buffer delays).
If the skew is large, most probably it is because it probably they are from different clock trees. In this case, you should try to separate the clock tree sources during scan insertion, and treat them as different clock domains.

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kbulusu

Joined: 23 Apr 2003
Posts: 133
Helped: 7

09 Feb 2007 19:07 pos edge flop

Shahal,
Lockup latches are always by default inserted even between two adjacent flops ( like between last flop of scan chain1 and first flop of scan chain2 )..this behaviour can controlled ofcourse..the reason tools do this is because..during placement, you cant guarntee that these flops will be close/adjacent physically ...this is one of the primary reason why LL are used...

[quote="shahal"]Dr Dft, let me ask a question. Lock up latches, ofcourse you use it to cross clock domain boundry. Would you use lock up Latches between adjacent flops if the clock was skew between the two flop clocks was greater than the data propagation path between the flops?

My understanding is yes you would, given the above criteria because the second flop will latch the new value of the first flop. Is my understanding correct or is this some how tool dependent and some tools will insert LLs and some wont?[/quote]

shahal

Joined: 11 Jan 2007
Posts: 50

09 Feb 2007 22:08 scan chain hold time problem

Thanks guys. The paper "10 comandments for a scan design" showed a LL being added between adjacent flops in chain with clock skew being greater than the path delay. Which makes sense if you look at the waveforms.

dft_guy

Joined: 19 Oct 2006
Posts: 114
Helped: 14
Location: USA

10 Feb 2007 19:49 scan chain violations

I think what dr_dft says here...

Quote:

If the skew is small, then you should leave it to the backend tool to fix the hold time violation (by adding buffer delays).
If the skew is large, most probably it is because it probably they are from different clock trees. In this case, you should try to separate the clock tree sources during scan insertion, and treat them as different clock domains.

...should be underscored - the hold-time violations should be fixed in the backend. This is common in scan paths, to have hold-time violations, since there is usually no logic (other than sometimes buffers or inverters) between flops. The router will usually re-order the scan chain to effectively put more wire (thus delay) in the scan path.

If the design is well-timed, I think the only place lock-up latches are necessary are between clock domains. The synthesis tool will do this automatically, with the right settings. It will also, if asked, place a LL at the end of each scan chain, which is sometimes handy if you'll be combining them at a higher level of hierarchy.

John
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